Background::
Higher power consumption raises chip temperature because it draws
more current from the power source, which directly affects how long the batteries survive in portable
devices. High temperature affects the dependability and functionality of a circuit, requiring
more complex packaging and cooling strategies. One of the most significant challenges in VLSI
design is power consumption. The power consumption of the circuit rises with both transistor density
and chip complexity. In addition, one of the essential building blocks of hardware in the majority
of VLSI applications and digital signal processing systems is the multiplier.
Aims and objective::
This study aimed to design and compare array multiplier, Vedic multiplier,
and Wallace tree multiplier using variable bit lengths.
Methodology::
In this paper, authors designed array multiplier, Vedic multiplier, and Wallace tree
multiplier using variable bit lengths. For comparison, the VIVADO tool was used to simulate and
synthesize multiplier outputs.
Results::
Wallace tree multipliers resulted in 31.153mW, 13.220mW, 4.099mW, and 0.988 mW of
power dissipation for 16-bit, 8-bit, 4-bit, and 2-bit, respectively. The best multiplier was designed
using different logic like AOI, OAI, NAND-NAND, and NOR-NOR and was compared based on
power dissipation. It was observed that 2.256mW power dissipation was observed for NOR-NOR
logic, which was minimal among other logics.
Conclusion::
The 4-bit Wallace multiplier using NOR-NOR logic was used for FPGA implementation,
which can be used in digital signal processing applications.