FPGA Hardware Research Articles

Initial-offset and amplitude control of multi-scroll attractor in a chaotic jerk system

Abstract With the gradual deepening of research on chaos, in order to flexibly apply chaos, offset boosting and amplitude control have become a hot topic. However, few people have studied chaotic systems with multi-scroll attractor under initial conditions.
This paper constructs and analyzes a simple four-dimensional chaotic system. Unlike other extension methods that modify the original seed system, this method does not make any changes to the original seed system, only adds a new variable in the extension dimension. It is found that the proposed system can achieve offset boosting and amplitude control by changing the initial values, and the system has characteristics such as multi-scroll attractors, infinite equilibrium points, symmetry, and so on. Finally, FPGA hardware implementation was carried out to verify the numerical results.

Beam Orbital Parameter Prediction Based on the Deployment of Cascaded Neural Networks at Edge Intelligence Acceleration Nodes

During the beam current calibration process, accurate guidance of the beam current to the metal target is a challenging issue for proton accelerators. To address this challenge, we propose the use of beam orbital parameters combined with reinforcement learning algorithms to achieve automatic beam calibration. This study introduces a system architecture that employs edge intelligent acceleration nodes based on deep learning acceleration techniques. We designed a system to predict BPM parameters using a cascaded backpropagation neural network (CBPNN) that is informed by the physical structure. This system serves as an environmental map for reinforcement learning, aiding beam current correction. The CBPNN was implemented on the acceleration node to hasten the forward inference process, leveraging sparsification, quantization algorithms, and pipelining techniques. Our experimental results demonstrated that the simulated inference speed reached 28 μs with FPGA hardware as the edge acceleration node, achieving forward inference speeds 35.66 and 12.66 times faster than those of the CPU and GPU. The energy efficiency ratio was 10.582 MOPS/W, which was 989 and 410 times that of the CPU and GPU, respectively. This confirms the designed architecture’s energy efficiency and low latency attributes.

Enhancing 2-D Electrical Impedance Tomography Throughput With a Combined FPGA and Edge GPU-Based Hardware Accelerator

Enhancing 2-D Electrical Impedance Tomography Throughput With a Combined FPGA and Edge GPU-Based Hardware Accelerator

A high speed pipelined radix-16 Booth multiplier architecture for FPGA implementation

Since multiplication is a complex and resource-consuming operation, it is very effective on the speed performance of a processor. In this regard, fast multiplication unit design is important in digital system architectures. FPGA hardware, which is efficient for the implementation and rapid prototyping of today’s digital system architectures, is becoming widespread. Therefore, in this study it aimed to design a fast radix-16 Booth multiplier based on the FPGA architecture. Booth multiplier implementation is preferred because it is relatively simple and efficient. The sizes of the multiplexers, which have an impact on the operating period in the encoder part of the proposed multiplier, reduced in the designed architecture by using a simple algorithm. To increase the speed performance of the system, the pipeline technique is used and parallelization is preferred in the tree structure in addition of the partial products. The effects of different multiplexer sizes, bit lengths and pipeline stages on the operating period of the system and other performance metrics examined. Different designs and the results obtained presented. According to the results, the multiplier hardware architectures designed in this study exhibit effective results in terms of speed performance.

FPGA hardware kit for remote training platforms

This paper outlines the development of a Hardware Development Kit (HDK) for a remote training platform on FPGA Devices designed to provide university students pursuing degrees in electronic and informatics engineering (at the bachelor’s, master’s, and PhD levels) with the tools they need to learn and develop systems related to artificial intelligence, digital signal processing, image processing, digital systems, integrated and embedded systems using an FPGA chip. Through the internet or a local network, students can engage with the platform to conduct engineering experiments. The HDK is equipped with a Raspberry Pi, a screen, a camera, and LEDs to facilitate the transfer of experiment results and to aid in assessing the validity of lab experiment execution. The Raspberry Pi plays a crucial role in the HDK, providing control and monitoring, remote access, data processing, user interface, and integration with other possible systems.

Dynamics and Implementation of FPGA for Memristor-Coupled Fractional-Order Hopfield Neural Networks

The coupling between neurons can lead to diverse neural network architectures, with the Hopfield neural network (HNN) being particularly noteworthy for its resemblance to human brain function and its potential in modeling chaotic systems. This paper introduces a novel approach: a fractional-order HNN coupled with a hyperbolic tangent-type memristor. Initially, we propose a new model for the hyperbolic tangent-type memristor and fingerprints. Subsequently, we construct a memristor-coupled fractional-order Hopfield neural network (mFOHNN) and explore its dynamic behavior using various analytical tools, including phase diagrams, bifurcation diagrams, Lyapunov exponent diagrams, Poincaré maps, and attractor basins. Our findings reveal rich coexisting bifurcation behavior in the neural network model, influenced by different initial values of coexisting attractors. Finally, we validate the model through analysis and implementation using Multisim circuit simulation software and FPGA hardware, respectively.

Localizing unknown nodes with an FPGA-enhanced edge computing UAV in wireless sensor networks: Implementation and evaluation

Great interest is directed toward real-time applications to determine the exact location of sensor nodes deployed in an area of interest. In this paper, we present a novel approach using a combination of the Kalman filter and regularized bounding box method for localizing unknown nodes in an area using an FPGA-enhanced edge computing UAV whose trajectory is known and is represented as the position of many anchors. The UAV is equipped with a GPS system that allows it to gather location data of sensor nodes as it moves around its environment. We employ a regularized bounding box to predict the positions of the unknown nodes using regularization factors and we use the Kalman filter algorithm to smooth and improve the accuracy of the sensor nodes to be localized. In order to localize the unknown nodes, the UAV receives the number of hops from each node and uses this information as input to the localization algorithm. Furthermore, the use of an FPGA board allows for real-time processing of sensory data, enabling the UAV to make fast and accurate decisions in dynamic environments. The localization algorithm was implemented on the FPGA board “Zynq MiniZed 7007s evaluation board” using Xilinx blocks in Simulink, and the generated code was converted into VHDL using Xilinx System Generator. The algorithm was simulated and synthesized using “Vivado” software. In fact, the proposed system was evaluated by comparing the performances achieved through two different implementations: Hardware and Software implementation. In effect, the performance of FPGA hardware implementation presents a new achievement in localization due to its easy testing and fast implementation. Our results show that this approach can efficiently locate unknown nodes with good latency and high accuracy. In fact, the execution time of the FPGA-integrated algorithm is reduced by about 60 times compared to the software implementation and the power consumption is about 100 mW, which proves the suitability of FPGA for localization in WSNs, offering a promising solution for various mobile WSN applications.

Design of FPGA-based data acquisition system for nanoparticle counting

Abstract As one of the effective means to monitor the environment, the number of particles in the air is gradually developing towards smaller nanoparticles. To improve the acquisition speed of nanoparticle signals and the count of the number of particle signals, this paper adopts the FPGA of Altera as the main control chip, combined with the high-speed ADC AD9280. The sampling of the particle pulse signal is realized, and the collected data is transmitted to the host computer through serial communication. Through the designed peak detection algorithm, the algorithm is hardware accelerated to realize real-time continuous processing of particle signal, calculate the number of peaks, and then get the number of particles. In this paper, the hardware circuit and FPGA logic design of the system are described, and the acquisition system is tested. The results show that the system can meet the requirements.

TinyM 2 Net-V2: A Compact Low-power Software Hardware Architecture for M ulti m odal Deep Neural Networks

With the evaluation of Artificial Intelligence (AI), there has been a resurgence of interest in how to use AI algorithms on low-power embedded systems to broaden potential use cases of the Internet of Things (IoT). To mimic multimodal human perception, multimodal deep neural networks (M-DNN) have recently become very popular with the classification task due to their impressive performance for computer vision and audio processing tasks. This article presents TinyM 2 Net-V2 —a compact low-power software hardware architecture for m ulti m odal deep neural networks for resource-constrained tiny devices. To compress the models to implement on tiny devices, cyclicly sparsification and hybrid quantization (4-bits weights and 8-bits activations) methods are used. Although model compression techniques are an active research area, we are the first to demonstrate their efficacy for multimodal deep neural networks, using cyclicly sparsification and hybrid quantization of weights/activations. TinyM 2 Net-V2 shows that even a tiny multimodal deep neural network model can improve the classification accuracy more than that of any unimodal counterparts. Parameterized M-DNN model architecture was designed to be evaluated in two different case-studies: vehicle detection from multimodal images and audios and COVID-19 detection from multimodal audio recordings. The most compressed TinyM 2 Net-V2 achieves 92.5% COVID-19 detection accuracy (6.8% improvement from the unimodal full precision model) and 90.6% vehicle classification accuracy (7.7% improvement from the unimodal full precision model). A parameterized and flexible FPGA hardware accelerator was designed as well for TinyM 2 Net-V2 models. To the best of our knowledge, this is the first work accelerating multimodal deep neural network models on low-power Artix-7 FPGA hardware. We achieved energy efficiency of 9.04 GOP/s/W and 15.38 GOP/s/W for case-study 1 and case-study 2, respectively, which is comparable to the state-of-the-art results. Finally, we compared our tiny FPGA hardware implementation results with off-the-shelf resource-constrained devices and showed our implementation is faster and consumed less power compared to the off-the-shelf resource-constrained devices.

FPGA Implementation of a PV Generator and a Boost Converter Controllers for a Virtual Laboratory Environment

This paper presents an FPGA hardware implementation of two different components of a microgrid’s electrical systems. Small and isolated microgrids are currently a frequent solution for electricity coverage in remote areas, where detailed studies, simulations, and realistic emulations are required to design appropriate systems according to each location. Hardware implementations based on a Labview environment of 240 W and 330 W generic photovoltaic generators, a Boost converter, and P &O algorithm were performed. The results obtained from the panels and converter were compared to the Simulink response. Unified systems, with and without controls, were compared. The systems were first compiled individually on an FPGA NI PCIe 7841R and later unified. The data and performance obtained from the emulated environment were verified using Simulink models, and the desired correspondence was obtained.

An evaluation research of constant false alarm rate algorithm for the application of underwater vehicles management system based on USBL sonar principles in shallow water

The paper presents an overview of underwater traffic management systems utilizing sonar principles. Based on the evaluation of the current situation both domestically and internationally, the research team has proposed the development of a underwater signal processing algorithm based on an adaptive threshold in the Ultra-short Baseline System (USBL). The theoretical results were implemented on FPGA hardware, not only enhancing signal detection capabilities but also meeting real-time signal processing requirements when deployed in complex underwater conditions in various shallow water regions of Vietnam. The research's future direction indicates substantial potential in the practical application of hydroacoustic signal processing algorithms when executing hardware implementations.

GS-AGC: An Adaptive Glare Suppression Algorithm Based on Regional Brightness Perception

Existing algorithms for enhancing low-light images predominantly focus on the low-light region, which leads to over-enhancement of the glare region, and the high complexity of the algorithm makes it difficult to apply it to embedded devices. In this paper, a GS-AGC algorithm based on regional luminance perception is proposed. The indirect perception of the human eye’s luminance vision was taken into account. All similar luminance pixels that satisfied the luminance region were extracted, and adaptive adjustment processing was performed for the different luminance regions of low-light images. The proposed method was evaluated experimentally on real images, and objective evidence was provided to show that its processing effect surpasses that of other comparable methods. Furthermore, the potential practical value of GS-AGC was highlighted through its effective application in road pedestrian detection and face detection. The algorithm in this paper not only effectively suppressed glare but also achieved the effect of overall image quality enhancement. It can be easily combined with the embedded hardware FPGA for acceleration to improve real-time image processing.

Automated Buffer Sizing of Dataflow Applications in a High-level Synthesis Workflow

High-Level Synthesis (HLS) tools are mature enough to provide efficient code generation for computation kernels on FPGA hardware. For more complex applications, multiple kernels may be connected by a dataflow graph. Although some tools, such as Xilinx Vitis HLS, support dataflow directives, they lack efficient analysis methods to compute the buffer sizes between kernels in a dataflow graph. This article proposes an original method to safely approximate such buffer sizes. The first contribution computes an initial overestimation of buffer sizes without knowing the memory access patterns of kernels. The second contribution iteratively refines those buffer sizes, thanks to cosimulation. Moreover, the article introduces an open source framework using these methods to facilitate dataflow programming on FPGA using HLS. The proposed methods and framework have been tested on seven dataflow applications and outperform Vitis HLS cosimulation in five benchmarks, either in terms of BRAM and LUT usage, or in terms of exploration time. In the two other benchmarks, our best method gets results similar to Vitis HLS. Last but not least, our method admits directed cycles in the application graphs.

A Binocular Stereo-Imaging-Perception System with a Wide Field-of-View and Infrared- and Visible Light-Dual-Band Fusion.

With the continuous evolution of autonomous driving and unmanned driving systems, traditional limitations such as a limited field-of-view, poor ranging accuracy, and real-time display are becoming inadequate to satisfy the requirements of binocular stereo-perception systems. Firstly, we designed a binocular stereo-imaging-perception system with a wide-field-of-view and infrared- and visible light-dual-band fusion. Secondly we proposed a binocular stereo-perception optical imaging system with a wide field-of-view of 120.3°, which solves the small field-of-view of current binocular stereo-perception systems. Thirdly, For image aberration caused by the wide-field-of-view system design, we propose an ellipsoidal-image-aberration algorithm with a low consumption of memory resources and no loss of field-of-view. This algorithm simultaneously solves visible light and infrared images with an aberration rate of 45% and 47%, respectively. Fourthly, a multi-scale infrared- and visible light-image-fusion algorithm is used, which improves the situational-awareness capabilities of a binocular stereo-sensing system in a scene and enhances image details to improve ranging accuracy. Furthermore, this paper is based on the Taylor model-calibration binocular stereo-sensing system of internal and external parameters for limit correction; the implemented algorithms are integrated into an NVIDIA Jetson TX2 + FPGA hardware framework, enabling near-distance ranging experiments. The fusion-ranging accuracy within 20 m achieved an error of 0.02 m, outperforming both visible light- and infrared-ranging methods. It generates the fusion-ranging-image output with a minimal delay of only 22.31 ms at a frame rate of 50 Hz.

Multi-criteria Optimization of Real-time DAGs on Heterogeneous Platforms under P-EDF

This article tackles the problem of optimal placement of complex real-time embedded applications on heterogeneous platforms. Applications are composed of directed acyclic graphs of tasks, with each directed-acyclic-graph (DAG) having a minimum inter-arrival period for its activation requests and an end-to-end deadline within which all of the computations need to terminate since each activation. The platforms of interest are heterogeneous power-aware multi-core platforms with Dynamic Voltage and Frequency Scaling (DVFS) capabilities, including big.LITTLE Arm architectures and platforms with GPU or FPGA hardware accelerators with Dynamic Partial Reconfiguration capabilities. Tasks can be deployed on CPUs using partitioned EDF-based scheduling. Additionally, some of the tasks may have an alternate implementation available for one of the accelerators on the target platform, which are assumed to serve requests in non-preemptive FIFO order. The system can be optimized by minimizing power consumption, respecting precise timing constraints, maximizing the applications’ slack, respecting given power consumption constraints, or even a combination of these, in a multi-objective formulation. We propose an off-line optimization of the mentioned problem based on mixed-integer quadratic constraint programming (MIQCP). The optimization provides the DVFS configuration of all the CPUs (or accelerators) capable of frequency switching and the placement to be followed by each task in the DAGs, including the software-vs.-hardware implementation choice for tasks that can be hardware accelerated. For relatively big problems, we developed heuristic solvers capable of providing suboptimal solutions in a significantly reduced time compared to the MIQCP strategy, thus widening the applicability of the proposed framework. We validate the approach by running a set of randomly generated DAGs on Linux under SCHED_DEADLINE, deployed onto two real boards, one with Arm big.LITTLE architecture, the other with FPGA acceleration, verifying that the experimental runs meet the theoretical expectations in terms of timing and power optimization goals.

Deployment of ML in Changing Environments

The High-Luminosity LHC upgrade of the CMS experiment will utilise a large number of Machine Learning (ML) based algorithms in its hardware-based trigger. These ML algorithms will facilitate the selection of potentially interesting events for storage and offline analysis. Strict latency and resource requirements limit the size and complexity of these models due to their use in a high-speed trigger setting and deployment on FPGA hardware. It is envisaged that these ML models will be trained on large, carefully tuned, Monte Carlo datasets and subsequently deployed in a real-world detector environment. Not only is there a potentially large difference between the MC training data and real-world conditions but these detector conditions could change over time leading to a shift in model output which could degrade trigger performance. The studies presented explore different techniques to reduce the impact of this effect, using the CMS track finding and vertex trigger algorithms as a test case. The studies compare a baseline retraining and redeployment of the model and episodic training of a model as new data arrives in a continual learning context. The results show that a continually learning algorithm outperforms a simple retrained model when degradation in detector performance is applied to the training data and is a viable option for maintaining performance in an evolving environment such as the High-Luminosity LHC.

ACT5 Electrical Impedance Tomography System.

This article introduces the Adaptive Current Tomograph 5 (ACT5) Electrical Impedance Tomography (EIT) system. ACT5 is a 32 electrode applied-current multiple-source EIT system that can display real-time images of conductivity and susceptivity at 27 frames per second. The adaptive current sources in ACT5 can apply fully programmable current patterns with frequencies varying from 5 kHz to 500 kHz. The system also displays real-time ECG readings during the EIT imaging process. The hardware and software design and specifications are presented, including the current source design, FPGA hardware, safety features, calibration, and shunt impedance measurement. Images of conductivity and susceptivity are presented from ACT5 data collected on tank phantoms and a human subject illustrating the system's ability to provide real-time images of pulsatile perfusion and ECG traces. The portability, high signal-to-noise ratio, and flexibility of applied currents over a wide range of frequencies enable this instrument to be used to obtain useful human subject data with relative clinical ease.

Research on developing an adaptive algorithm for enhancing the quality of underwater positioning based on the sonar USBL principle

The paper proposes an enhanced solution for improving the accuracy of underwater object positioning based on the Ultra-Short Baseline (USBL) sonar principle. In shallow water regions, complex hydrological phenomena affect the quality of underwater acoustic signal transmission and reception, making it essential to enhance the processing of these signal groups. Through the USBL system model, the paper presents a model capable of adaptively selecting accurate signals amidst the noisy underwater environment. The proposed model is implemented and validated in practice using FPGA hardware in Lan Ha Bay. The results demonstrate the effectiveness of the proposed algorithm compared to conventional approaches, as it extends the management range and optimizes the transmission power of the system, even in cases of low signal-to-noise ratio.

FlowPix: Accelerating Image Processing Pipelines on an FPGA Overlay using a Domain Specific Compiler

The exponential performance growth guaranteed by Moore’s law has started to taper in recent years. At the same time, emerging applications like image processing demand heavy computational performance. These factors inevitably lead to the emergence of domain-specific accelerators (DSA) to fill the performance void left by conventional architectures. FPGAs are rapidly evolving towards becoming an alternative to custom ASICs for designing DSAs because of their low power consumption and a higher degree of parallelism. DSA design on FPGAs requires careful calibration of the FPGA compute and memory resources towards achieving optimal throughput. Hardware Descriptive Languages (HDL) like Verilog have been traditionally used to design FPGA hardware. HDLs are not geared towards any domain, and the user has to put in much effort to describe the hardware at the register transfer level. Domain Specific Languages (DSLs) and compilers have been recently used to weave together handwritten HDLs templates targeting a specific domain. Recent efforts have designed DSAs with image-processing DSLs targeting FPGAs. Image computations in the DSL are lowered to pre-existing templates or lower-level languages like HLS-C. This approach requires expensive FPGA re-flashing for every new workload. In contrast to this fixed-function hardware approach, overlays are gaining traction. Overlays are DSAs resembling a processor, which is synthesized and flashed on the FPGA once but is flexible enough to process a broad class of computations through soft reconfiguration. Less work has been reported in the context of image processing overlays. Image processing algorithms vary in size and shape, ranging from simple blurring operations to complex pyramid systems. The primary challenge in designing an image-processing overlay is maintaining flexibility in mapping different algorithms. This paper proposes a DSL-based overlay accelerator called FlowPix for image processing applications. The DSL programs are expressed as pipelines, with each stage representing a computational step in the overall algorithm. We implement 15 image-processing benchmarks using FlowPix on a Virtex-7-690t FPGA. The benchmarks range from simple blur operations to complex pipelines like Lucas-Kande optical flow. We compare FlowPix against existing DSL-to-FPGA frameworks like Hetero-Halide and Vitis Vision library that generate fixed-function hardware. On most benchmarks, we see up to 25% degradation in latency with approximately a 1.7x to 2x increase in the FPGA LUT consumption. Our ability to execute any benchmark without incurring the high costs of hardware synthesis, place-and-route, and FPGA re-flashing justifies the slight performance loss and increased resource consumption that we experience. FlowPix achieves an average frame rate of 170 FPS on HD frames of 1920 × 1080 pixels in the implemented benchmarks.

Design, Calibration, and Evaluation of Real-Time Waveform Matching on an FPGA-based Digitizer at 10 GS/s

Digitizing side-channel signals at high sampling rates produces huge amounts of data, while side-channel analysis techniques only need those specific trace segments containing Cryptographic Operations (COs). For detecting these segments, waveform-matching techniques have been established comparing the signal with a template of the CO’s characteristic pattern. Real-time waveform matching requires highly parallel implementations as achieved by hardware design but also reconfigurability as provided by FPGAs to adapt the matching hardware to a specific CO pattern. However, currently proposed designs process the samples from analog-to-digital converters sequentially and can only process low sampling rates due to the limited clock speed of FPGAs. In this paper, we present a parallel waveform-matching architecture capable of performing high-speed waveform matching on a high-end FPGA-based digitizer. We also present a workflow for calibrating the waveform-matching system to the specific pattern of the CO in the presence of hardware restrictions provided by the FPGA hardware. Our implementation enables waveform matching at 10 GS/s, offering a speedup of 50x compared to the fastest state-of-the-art implementation known to us. We demonstrate how to apply the technique for attacking the widespread XTS-AES algorithm using waveform matching to recover the encrypted tweak even in the presence of so-called systemic noise.