FPGA-based Test Bed Research Articles

SATMAC: Self-Adaptive TDMA-Based MAC Protocol for VANETs

Rapid development and deployment of vehicular ad-hoc networks (VANETs) require an efficient and scalable media access control (MAC) protocol to support high-priority safety applications and infotainment requirements. This paper proposes SATMAC, a self-adaptive time division multiple access (TDMA)-based MAC protocol for VANETs. In order to improve the stability of the time slot scheduling in VANETs, a slot status updating strategy is carefully designed, which utilizes accurate information of the two-hop neighbors and the rough information of the three-hop neighbors to detect the potential packet collisions and avoids potential collisions by adjusting the occupied time slot. Besides, an adaptive frame length (the number of time slots contained in a frame) approach is proposed on the basis of the slot adjustment to support various densities of vehicles, where the frame length between neighbors can be inconsistent. We conduct theoretical analysis and extensive simulations in a realistic VANET environment to evaluate SATMAC. Simulation results show that compared with IEEE 802.11p and LTE-V2X PC5 Mode 4, SATMAC significantly improves PDR of beacons over 60%. Moreover, our SATMAC design is further implemented and validated on our FPGA-based testbed.

A Digital-Domain Controlled Nonlinear RF Interference Cancellation Scheme for Co-Site Wideband Radios

In this paper, a digital-domain reconstruction based radio-frequency (RF) interference cancellation scheme is proposed to cancel the nonlinear wideband self-interference (SI) signal in co-site radio systems. First, an auxiliary cancellation chain is employed to reconstruct and suppress the SI signal received at the receiver chain. Then, in order to generate the SI replica more accurately, we derive two nonlinear models to predicate the coupling characteristics for the nonlinear wideband SI signal. The proposed models combine the transmit chain and wireless SI channel characteristics, and employ both the Hammerstein model and Wiener model for the transmit chain, respectively. Next, the coefficients of each linear and nonlinear component in the SI chain are integrated into a coefficient vector, which is linear with respect to the output samples, with the proposed models. Based on the linearity, a dynamic least-squares (LS) type algorithm is developed to efficiently estimate and update the coefficients of the proposed models. Finally, experimental results obtained from a FPGA-based testbed have validated that the proposed scheme has a superior interference cancellation performance for nonlinear wideband SI.

Fault Injection Test Bed for Clock Violation

In this paper, the International Data Encryption (IDEA) algorithm synthesis models will be used as test encryption algorithm. The Xilinx Digital clock manager component will be used for generation of clocks for different frequencies and phase shifts. The encryption output with faults introduced and without faults introduced is compared as a function of ratio of used clock frequency and maximum frequency of operation reported by synthesis tool. The clock generation, clock switching, interface adopter to IDEA core and UART interface will be realized and tested in FPGA hardware in integrated form. FPGA based test bed is realized for injecting faults through clock glitches, to result in setup and hold violations. The UART interface is realized on FPGA to provide PC based controlling for this fault injection. Xilinx chip scope tools will be used for verifying the output at various levels in FPGA hardware.

원자력발전소 안전계통용 고신뢰성 MVB 네트워크 구현

The computer network plays an important role in modern digital controllers within a safety system of a nuclear power plant. For the reliable and realtime data communication between controllers, this paper proposes a modified high-reliable MVB(multi-function vehicle bus) as a main control network for a safety system of a nuclear power plant. The proposed network supports the state-based communication in order to ensure the deterministic communication latency, and very fast network recovery when the bus master fails compare to the standard MVB. This paper also shows the implementation results using a FPGA-based testbed.