FPGA-based Soft-core Processors Research Articles

Customized FPGA Design and Analysis of Soft-Core Processor for DNN

Transistor scaling has continued to yield significant performance gains. The general-purpose architecture will not suffice in this dark silicon era with the big data boom and growing emphasis on performance. Artificial neural networks and deep learning are sophisticated computing activities that cannot be optimally executed (accuracy, performance, and energy) on today's general-purpose computer architecture. The demand for domain-specific computer architectures is increasing. This paper suggests and evaluates a highly reconfigurable domain-specific design for deep learning and artificial neural networks to overcome these problems. An FPGA-based soft-core processor for deep neural network (DNN) acceleration is suggested in this paper. Using a combination of unicast and multicast for collective operations, the proposed FPGA accelerates the performance of the deep learning network. The suggested design outperforms the current general-purpose processor by 6.6 times, according to a thorough examination and comparison. The existing architecture's level of accuracy is retained.

Field Programmable Gate Array Softcore Processors Optimised for Digital Signal Processing Applications

The benefits of adding explicit DSP operation support to an FPGA-based softcore processor are examined. An experimental DSP processor has been designed, implemented, simulated, and verified on a Xilinx Virtex-5 XC5VSX50T FPGA chip. An initial very simple architecture is upgraded with different supporting hardware to enhance the processor's performance in execution of DSP applications. These hardware enhancement techniques include a specialist execution unit, modification to the memory architecture, adding an extra address control unit, upgrading with more active addressing modes, and extending the instruction set with zero-overhead looping support. These enhancements reduce the number of instructions used in the inner loop of convolution-based DSP algorithms to a single instruction. By using these proposed enhancement techniques, the overall performance was improved by an average of 9 times (800% improvement) in FIR Filter and Matrix Multiplication benchmark DSP applications. The overall area increased by about 1.41 times (41% extra cost). Using in-built DSP blocks in the FPGA instead of logic blocks to implement the arithmetic unit of the processor reduced the power consumption by 14% from 840 mW to 725 mW.

FPGA-Based Soft-Core Processors for Image Processing Applications

With security and surveillance, there is an increasing need to process image data efficiently and effectively either at source or in a large data network. Whilst a Field-Programmable Gate Array has been seen as a key technology for enabling this, the design process has been viewed as problematic in terms of the time and effort needed for implementation and verification. The work here proposes a different approach of using optimized FPGA-based soft-core processors which allows the user to exploit the task and data level parallelism to achieve the quality of dedicated FPGA implementations whilst reducing design time. The paper also reports some preliminary progress on the design flow to program the structure. An implementation for a Histogram of Gradients algorithm is also reported which shows that a performance of 328 fps can be achieved with this design approach, whilst avoiding the long design time, verification and debugging steps associated with conventional FPGA implementations.

A Fault Tolerant Design Methodology for a FPGA-based Softcore Processor

The susceptibility of digital systems to faults requires the implementation of Fault Tolerant architectures to ensure high-reliability and availability. Field Programmable Gate Arrays are especially sensitive to Single-Event Upsets and Single-Event Transients, since the configuration memory of the chip can be affected, resulting in permanent error; thus, special care must be taken when implementing Fault Tolerant architectures for FPGAs. This paper describes the architecture of a Fault Tolerant softcore processor using triplication of all units as well as using a parity protection scheme for on-chip caches, presenting the impact on area, clock frequency and I/O requirements of both implementations, targeting FPGAs. Experiments show a high fault tolerance and demonstrate the relationship of cache hit rates with fault propagation.