FPGA-based DSP Research Articles

High-Speed Energy-Efficient Fixed-Point Signed Multipliers for FPGA-Based DSP Applications

High-Speed Energy-Efficient Fixed-Point Signed Multipliers for FPGA-Based DSP Applications

Real-Time Demonstration of Concurrent Upstream and Inter-ONU Communications in Hybrid OFDM DFMA PONs

This letter presents the first real-time experimental demonstration of concurrent upstream and inter-ONU communications in a hybrid OFDM DFMA PON, enabled by a simple low-cost alteration to the remote node. Real-time FPGA-based DSP, incorporating a 128-pt FFT and a joint sideband processing technique, is used to demultiplex different sub-wavelength channels at the ONU and OLT receivers. The simple modification in the remote node removes the need for direct user-to-user data to pass via the OLT and core network thus providing ultra-low latency inter-ONU connectivity to support a variety of newly emerging latency sensitive 5G services. The presented PON is validated with two subwavelength bands, each capable of carrying one of two possible orthogonal channels ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$I$ </tex-math></inline-formula> or <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> ). The dynamic channel and subcarrier allocation allows flexible allocation of PON capacity between upstream and inter-ONU links for dynamic on-demand capacity allocation and also performance optimisation according to the different length dependent link characteristics. Moreover, the backscattering effect associated with upstream signals is shown to have negligible effect on the BER performance of the inter-ONU communications.

Reliability Models for SEC/DED Memory With Scrubbing in FPGA-Based Designs

Block RAMs on field-programmable gate arrays (FPGAs) are susceptible to radiation-induced single-event upsets (SEUs) and are usually protected by fault-tolerant techniques such as single error correction/double error correction (SEC/DED) codes and/or scrubbing. Scrubbing can be divided into two categories based on the mechanism that controls the scrubbing interval. With deterministic scrubbing, each memory location is scrubbed (repaired) on a regular basis and the interval is fixed. With probabilistic scrubbing, a word is checked and corrected any time it is accessed (read or written). In this case, the scrubbing interval is exponentially distributed. This paper presents two mean-time-to-failure (MTTF) models for SEC/DED memory with scrubbing, which can be applied to general applications, including FPGA designs. The first one considers only probabilistic scrubbing but takes into account nonuniform scrub rates for different memory locations. The second model combines both deterministic scrubbing and probabilistic scrubbing into a single model. The proposed models provide more accurate MTTF estimates compared with prior models. An FPGA-based DSP application is studied as an example to show how the proposed models can be used for estimating memory reliability and to reveal the impact of probabilistic scrub rates and memory access distributions on memory reliability.

Experimental demonstrations of record high REAM intensity modulator-enabled 1925Gb/s real-time end-to-end dual-band optical OFDM colorless transmissions over 25km SSMF IMDD systems

Record-high 19.25Gb/s real-time end-to-end dual-band optical OFDM (OOFDM) colorless transmissions across the entire C-band are experimentally demonstrated, for the first time, in reflective electro-absorption modulator (REAM)-based 25km standard SMF systems using intensity modulation and direct detection. Adaptively modulated baseband (0-2GHz) and passband (6.125 ± 2GHz) OFDM RF sub-bands, supporting signal line rates of 9.75Gb/s and 9.5Gb/s respectively, are independently generated and detected with FPGA-based DSP clocked at only 100MHz as well as DACs/ADCs operating at sampling speeds as low as 4GS/s. The two OFDM sub-bands are electrically multiplexed for intensity modulation of a single optical carrier by an 8GHz REAM. The REAM colorlessness is experimentally characterized, based on which optimum REAM operating conditions are identified. To maximize and balance the signal transmission performance of each sub-band, on-line adaptive transceiver optimization functions and live performance monitoring are fully exploited to optimize key OOFDM transceiver and system parameters. For different wavelengths within the C-band, corresponding minimum received optical powers at the FEC limit vary in a range of <0.5dB and bit error rate performances for both baseband and passband signals are almost identical. Furthermore, detailed investigations are also undertaken of the maximum aggregated signal line rate sensitivity to electrical sub-band power variation. It is shown that the aforementioned system has approximately 3dB tolerance to RF sub-band power variation.

Experimental demonstration of record high 19125Gb/s real-time end-to-end dual-band optical OFDM transmission over 25km SMF in a simple EML-based IMDD system

Record high 19.125 Gb/s real-time end-to-end dual-band optical OFDM (OOFDM) transmission is experimentally demonstrated, for the first time, in a simple electro-absorption modulated laser (EML)-based 25 km standard SMF system using intensity modulation and direct detection (IMDD). Adaptively modulated baseband (0-2GHz) and passband (6.125 ± 2GHz) OFDM RF sub-bands, supporting line rates of 10 Gb/s and 9.125 Gb/s respectively, are independently generated and detected with FPGA-based DSP clocked at only 100 MHz and DACs/ADCs operating at sampling speeds as low as 4GS/s. The two OFDM sub-bands are electrically frequency-division-multiplexed (FDM) for intensity modulation of a single optical carrier by an EML. To maximize and balance the signal transmission performance of each sub-band, on-line adaptive features and on-line performance monitoring is fully exploited to optimize key OOFDM transceiver and system parameters, which includes subcarrier characteristics within each individual OFDM sub-band, total and relative sub-band power as well as EML operating conditions. The achieved 19.125 Gb/s over 25 km SMF OOFDM transmission system has an optical power budget of 13.5 dB, and shows almost identical bit error rate (BER) performances for both the baseband and passband signals. In addition, experimental investigations also indicate that the maximum achievable transmission capacity of the present system is mainly determined by the EML frequency chirp-enhanced chromatic dispersion effect, and the passband BER performance is not affected by the two sub-band-induced intermixing effect, which, however, gives a 1.2dB optical power penalty to the baseband signal transmission.

IMPLEMENTING AN OFDM SYSTEM ON HARDWARE

Recently, OFDM technique has been applied to many digital communications systems such as DVB-T, WiFi, WiMAX and MIMO systems. OFDM can send multiple high speed signals by using orthogonal carrier frequencies. In addition, OFDM technique can combat inter-symbol interference (ISI) and inter-channel interference (ICI). Therefore, OFL has been an essential technology in high-speed communications. The aim of this project is to implement the base-band OFDM system on hardware exploiting FPGA-based DSP Development Kit and DSPBuilder® software from Altera®. The results can be used for training purpose and for a further development of OFDM-based communication systems.

Optimization techniques for FPGA-based wave-pipelined DSP blocks

In this paper, techniques for efficient implementation of field-programmable gate-array (FPGA)-based wave-pipelined (WP) multipliers, accumulators, and filters are presented. A comparison of the performance of WP and pipelined systems has been made. Major contributions of this paper are development of an on-chip clock generation scheme which permits finer tuning of the frequency, a synthesis technique that reduces the area and latency by 25%, a placement utility that results in 10%-40% increase in speed and proposal of an interleaving scheme for filters that reduces the number of multipliers required by 50%. WP multipliers of size 2 /spl times/ 6 and the filters using them are found to be 11% faster and require lower power than those using pipelined multipliers. Filters with higher order WP multipliers also operate with lower power at the cost of speed. The delay-register products of such filters are found to be about 60% lower than those using the pipelined multipliers. The paper also outlines applications of these techniques for the Spartan II FPGAs and a self-tuning scheme for optimizing the speed.

Logic Foundry: Rapid Prototyping for FPGA-Based DSP Systems

We introduce the Logic Foundry, a system for the rapid creation and integration of FPGA-based digital signal processing systems. Recognizing that some of the greatest challenges in creating FPGA-based systems occur in the integration of the various components, we have proposed a system that targets the following four areas of integration: design flow integration, component integration, platform integration, and software integration. Using the Logic Foundry, a system can be easily specified, and then automatically constructed and integrated with system level software.

Configurable logic for digital communications: some signal processing perspectives

For the past two decades software programmable digital signal processors and ASICs have provided hardware solutions for signal processing system designers. A new option has become available: field programmable gate arrays. FPGA-based DSP platforms allow the designer to realize a data path that exactly matches the required processing, while at the same time maintaining the flexibility of a software approach. This article presents an overview of some FPGA DSP applications. Several filter designs are presented, and the use of CORDIC arithmetic for constructing an FPGA carrier recovery loop is outlined. In addition to presenting design examples that can be realized using present-generation devices and tools, we take a brief look at how the dynamic reconfiguration aspect of certain FPGAs could be exploited in future-generation communication technologies.