Fourth-order Modulator Research Articles

A 0.032-mm2 43.3-fJ/Step 100–200-MHz IF 2-MHz Bandwidth Bandpass DSM Based on Passive N-Path Filters

In this article, we demonstrate a bandpass (BP) delta–sigma modulator (DSM) using passive $N$ -path filters to implement resonators for high power efficiency, wide intermediate-frequency (IF) tuning range, and small area. The fourth-order modulator loop requires only one active element: an open-loop amplifier. The input magnitude of the amplifier is small due to the modulator’s global negative feedback and the passive $N$ -path filter preceding it. This lowers the power consumption of the amplifier and relaxes the design constraints of the switches in the $N$ -path filter. A system model of the linear periodically time-variant structure of the proposed modulator is developed, and its nonidealities are analyzed. A BP DSM prototype realized in a 65-nm CMOS with an active area of 0.032 mm2 features an IF tunable from 100 to 200 MHz with a sampling frequency ranging from 400 to 800 MHz. Over a fixed 2-MHz bandwidth, the modulator achieves a signal to noise and distortion ratio (SNDR) greater than 55.5 dB over the entire IF range. A maximal SNDR of 60.5 dB is achieved at 175-MHz IF while consuming 150 $\mu \text{W}$ , which corresponds to a Walden’s and Schreier’s figure of merits of 43.3 fJ/conv-step and 164.4 dB, respectively.

A High-Dynamic-Range Switched-Capacitor Sigma-Delta ADC for Digital Micromechanical Vibration Gyroscopes.

This paper presents a multi-stage noise shaping (MASH) switched-capacitor (SC) sigma-delta (ΣΔ) analog-to-digital converter (ADC) composed of an analog modulator with an on-chip noise cancellation logic and a reconfigurable digital decimator for MEMS digital gyroscope applications. A MASH 2-1-1 structure is employed to guarantee an absolutely stable modulation system. Based on the over-sampling and noise-shaping techniques, the core modulator architecture is a cascade of three single-loop stages containing feedback paths for systematic optimization to avoid deterioration in conversion accuracy caused by capacitor mismatch. A digital noise cancellation logic is also included to eliminate residual quantization errors in the former two stages, and those in the last stage are shaped by a fourth-order modulation. A multi-rate decimator follows the analog modulator to suit variable gyroscope bandwidth. Manufactured in a standard 0.35 μm CMOS technology, the whole chip occupies an area of 3.8 mm2. Experimental results show a maximum signal-to-noise ratio (SNR) of 100.2 dB and an overall dynamic range (DR) of 107.6 dB, with a power consumption of 3.2 mW from a 5 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 165.6 dB.

Two-micron all-fibered dual-comb spectrometer based on electro-optic modulators and wavelength conversion

Mid-infrared dual-comb spectroscopy offers interesting applications since molecules have their strongest rotational–vibrational absorptions in this frequency domain. Besides, generating frequency combs with electro-optic modulators recently showed promising results toward dual-comb spectroscopy. Here, we report a conversion in the mid-infrared of two mutually coherent frequency combs generated with electro-optic modulators to perform dual-comb spectroscopy in this region. Using fourth-order modulation instability taking place in the normal dispersion regime of a highly nonlinear fiber and by seeding this phenomenon with a frequency agile and low-power laser around 1.3 μm, we develop a stable and wavelength tunable all-fibered dual-comb spectrometer operating in the 2 μm region. This allows us to investigate CO2 absorption spectra over 37 nm and to measure collisional broadening coefficients of a few rotational–vibrational lines.

A RE-CONFIGURABLE ARCHITECTURE FOR SWITCHED CAPACITOR SIGMA-DELTA ANALOG-TO-DIGITAL CONVERSION

A re-configurable switched capacitor sigma-delta analog-to-digital conversion architecture1,2 is proposed. The architecture consists of a MASH sigma delta modulator with nth lower-order (first- or second-order) loops cascaded together. Each loop can be powered on or off operating in high or low performance mode, according to application needs. The architecture can be configured to optimize performance and power consumption for specific resolution and applications. The architecture is proven by means of a prototype, implemented as a fourth-order and fabricated in a standard 0.18 um CMOS technology. The outputs of both high performance mode (fourth-order) and medium performance mode (second-order, first loop ON) are measured to demonstrate the configurability. The FFT demonstrates that the noise shaping for the fourth-order modulator is better than that of the second-order modulator with steeper noise shaping slope.

Active reduction of fluctuations in fourth-order modulation instability

We experimentally study the fluctuation properties of a scalar fourth-order modulation instability (MI) process obtained by pumping a photonic crystal fiber in the normal dispersion region. We observe large wavelength-dependent pulse-to-pulse fluctuations that cannot be significantly reduced by stimulating the process with a single seed. Their reduction requires two seeds slightly detuned from the maximum gain frequency in order to also stimulate the second-order MI process cascaded from the fourth-order one. This concept is validated by experiments and numerical simulations.

Multimode Reconfigurable Digital $\Sigma\Delta$ Modulator Architecture for Fractional-$N$ PLLs

This brief presents the analysis, design, and implementation of a multimode reconfigurable digital Sigma-Delta (ΣΔ) modulator for use in fractional- <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">N</i> phase-locked loops. Analysis of second-, third-, and fourth-order modulators with respect to PLL phase noise contribution in the presence of loop nonlinearities is performed. Optimal architectures in each order are found and a single reconfigurable modulator is designed and implemented on FPGA. The proposed architecture is able to cover seven different modes of operation and spans three orders, thus offering a great degree of noise-shaping flexibility suitable for multistandard wireless applications. A case study for LTE/WiMAX is further presented for demonstration.

A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops

A finite-modulo fractional-N PLL utilizing a low-bit high-order DeltaSigma modulator is presented. A 4-bit fourth-order DeltaSigma modulator not only performs non-dithered 16-modulo fractional-N operation but also offers less spur generation with negligible quantization noise. Further spur reduction is achieved by charge compensation in the voltage domain and phase interpolation in the time domain, which significantly relaxes the dynamic range requirement of the charge pump compensation current. A 1.8-2.6 GHz fractional-N PLL is implemented in 0.18 mum CMOS. By employing high-order deterministic DeltaSigma modulation and hybrid spur compensation, the spur level of less than -55 dBc is achieved when the ratio of the bandwidth to minimum frequency resolution is set to 1/4. The prototype PLL consumes 35.3 mW in which only 2.7 mW is consumed by the digital modulator and compensation circuits.

74 dB SNDR Multi-Loop Sturdy-MASH Delta-Sigma Modulator Using 35 dB Open-Loop Opamp Gain

This paper presents a new multi-loop delta-sigma modulator which overcomes the necessity of high DC gain opamps that were needed in previous multi-loop modulators. Enabling the use of low gain opamps also allows low-voltage operation due to the reduced number of transistors between the power supply rails. In addition, all the digital filters are removed from the output of this modulator to minimize the overall system requirement. Instead, an in-loop digital addition facilitates the desired noise transfer functions of both loops. This combines stability advantage of the multi-loop structure with relaxed circuit requirement of the single-loop modulator. A fourth order modulator is implemented in a 0.18 mum CMOS technology to demonstrate this concept. Measurement results show that, with open-loop opamp gain of less than 35 dB, the implemented prototype IC achieves over 74 dB SNDR at an oversampling ratio of 16. The sampling frequency is 20 MHz and the total power dissipation is 3.2 mW at 1.2 V supply.

Parallel Continuous-Time $\Delta\Sigma$ ADC for OFDM UWB Receivers

A parallel multibit continuous-time (CT) DeltaSigma analog-to-digital converter for an orthogonal-frequency-division-multiplexing (OFDM) ultrawideband receiver intended to operate according to the IEEE 802.15.3a or the ECMA 368 (ISO/IEC 26907) standards has been designed. The overall CT DeltaSigma converter consists of two modulators covering two unequal subbands (low-pass (LP) and bandpass (BP) subbands) that are arranged to operate in parallel and whose respective noise transfer functions (NTFs) are designed to match its corresponding frequency band. The composite NTF for the overall converter is defined as the minimum gain value out of these two individual NTFs. The LP and BP subbands were designed by using third- and fourth-order modulators, respectively, based on a 3-bit quantizer and operating at a clock frequency of 1056 MHz. NTF zero locations were optimized according to the criterion that all the in-band composite NTF gain maxima have approximately the same value. Combining OFDM signal characteristics and converter parameters, the effect of the quantization noise on the overall converter performance has been analytically derived. A simulation program has been realized to verify the performance of the converter.

Comparison of Bandpass $\Sigma\Delta$ Modulator Coding Efficiency With a Periodic Signal Model

Maximizing coding efficiency is important in applications where bandpass SigmaDelta modulation is used as a source encoder to synthesize a two-level pulse train in RF class-D amplifiers. A periodic pulse-train model is developed to MIMIC the encoding of a bandpass SigmaDelta modulator for sinusoidal source signals, and it is shown that the coding efficiency of both the model and the modulator vary similarly with changes in carrier oversample ratio. The relationship between coding efficiency and carrier oversample ratio is not monotonic and has significant dips at certain ratios. The predictions of the model are compared with simulation results for a fourth-order bandpass modulator. The results show that coding efficiency is low in a modulator design where the input frequency is one-fourth the sample rate (fs) and can be increased by as much as 15% by selecting a slightly lower oversample ratio such as (3/10)fs.

Bandpass Sigma&amp;ndash;Delta Modulator Employing SAW Resonator as Loop Filter

Continuous-time bandpass (BP) sigma-delta modulators (SigmaDeltaMs) employing surface acoustic wave (SAW) resonators as loop filters are presented. Compared with the loop filters realized with Gm-C and LC resonators, the SAW resonator has the advantage of high-Q factor, wide resonant frequency range and accurate resonant frequency without the need for automatic tuning. With the proposed anti-resonance cancellation and loop filter phase compensation techniques, a second- and a fourth-order BP SigmaDeltaMs are demonstrated in a 0.35-mum CMOS technology. Both modulators are tested with 47.3-MHz off-chip SAW resonators. The second-order modulator attains a dynamic range of 57 dB and peak signal-to-noise distortion ratio (SNDR) of 54 dB and the fourth-order one achieves a dynamic range of 69 dB and peak SNDR of 66 dB, both in a 200-kHz signal bandwidth. The fourth-order modulator is also measured in a 3.84-MHz signal bandwidth and achieves a dynamic range of 52.5 dB and peak SNDR of 50 dB, an effective 8-bit resolution

Low power delta-sigma Modulator for ADSL applications in a low-Voltage CMOS technology

This paper examines the design and implementation of a fourth-order low-pass delta-sigma modulator using a systematic top-down design methodology. Special effort has been made to reduce the power consumption of the modulator through careful system-level modeling and synthesis of circuit specifications. Tradeoffs between circuit building block specifications, optimization time and computing resources are derived. This system-level modeling was tested through the successful implementation of a switched-capacitor delta-sigma analog-to-digital converter integrated circuit (IC) with an output rate slightly exceeding 2 MS/s, in a 1.8-V 0.18-/spl mu/m, single-polysilicon six-metal standard CMOS process. When sampled at 50 MHz, experimental results reveal that the IC achieves 77.6-dB dynamic range. The prototype consumes 18.8 mW of power, making it one of the lowest power dissipations in switched-capacitor implementations, and for applications where output rates exceed 2 MS/s. When compared to other state-of-the-art switched-capacitor modulators using a widely adopted figure of merit, the modulator dissipates less power and offers superior overall performance.

Design of fourth-order ΔΣ modulator for the D/A conversion of audio signals

Abstract This paper describes an efficient circuit technique to minimize the hardware consumption for a digital fourth-order single loop ΔΣ modulator. The modulator employs a simple bit-shifting and the ROM selection scheme for multiplications and the new buffer-and-routing ROM structure. Fabricated in a standard digital 0.35 μm CMOS technology, the modulator achieves a signal-to-noise ratio (SNR) of 96 dB with an oversampling ratio of 256 under the supply of 2.0 V.

A 250-khz 94-db double-sampling ΣΔ modulation a/d converter with a modified noise transfer function

This paper presents a high-order double-sampling single-loop /spl Sigma//spl Delta/ modulation analog-to-digital (A/D) converter. The important problem of noise folding in double-sampling circuits is solved here at the architectural level by placing one of the zeros in the modulator's noise transfer function at half the sampling frequency instead of in the baseband. The resulting modulator is of fifth order but has the baseband performance of a fourth-order modulator. Through the use of an efficient switched-capacitor implementation, the overall circuit uses only four operational amplifiers and hence, its complexity is similar to that of a fourth-order modulator. An experimental 1-bit modulator was designed for an oversampling ratio of 96 and a bandwidth of 250 kHz at a 3.3-V supply in a conservative 0.8-/spl mu/m standard CMOS process. Due to the double-sampling, the sampling frequency is 48 MHz, although the circuits operate at a clock frequency of only 24 MHz. The circuit achieves a dynamic range of 94 dB. The peak signal-to-noise ratio and signal-to-noise-plus-distortion ratio were measured to be 90 and 86 dB, respectively. The power consumption of the complete circuit including clock drivers and output pad drivers was 43 mW. The analog blocks (opamps, comparators, etc.) consume 30 mW of this total.

14-bit 2.2-MS/s sigma-delta ADC's

This paper presents the design and test results of a fourth-order and sixth-order 14-bit 2.2-MS/s sigma-delta analog-to-digital converter (ADC). The analog modulator and digital decimator sections were implemented in a 0.35 /spl mu/m CMOS double-poly triple-level metal 3.3-V process. The design objective for these ADC's was to achieve 85 dB signal-to-noise distortion ratio (SNDR) with less than 200 mW power dissipation. Both modulators employ a cascade sigma-delta topology. The fourth-order modulator consists of two cascaded second-order stages which include 1-bit and 5-bit quantizers, respectively. The sixth-order modulator has a 2-2-2 cascade structure and 1-bit quantizer at the end of each stage. An oversampling ratio of 24 was selected to give the best SNDR and power consumption with realizable gain-matching requirements between the analog and digital sections.

On the design of a fourth-order continuous-time LC delta-sigma modulator for UHF A/D conversion

We consider the design and test of a fourth-order bandpass delta-sigma modulator (/spl Delta//spl Sigma/M) for conversion of UHF analog signals to the digital domain for heterodyning and processing there. A prototype modulator in 0.5-/spl mu/m SiGe presented in the second part of the paper achieved 40 dB of dynamic range in a 20-MHz bandwidth centered at 1 GHz and consumed 450 mW from a single 5-V supply. At the time this modulator was designed, no explicit design procedure to achieve a certain modulator performance level had been established. The first part of this paper, therefore, is devoted to explaining the tradeoffs involved in choosing the parameters for a gigahertz-clocking transconductor/LC-based /spl Delta//spl Sigma/M and formulating such an explicit design procedure. Finally, we elucidate some further design considerations, redesign the prototype to improve its simulated performance, and discuss the general appropriateness of high-speed continuous-time /spl Delta//spl Sigma/M for UHF analog-to-digital conversion.

Dynamic range extension technique for high-order ADCs by digital level control

A new architecture is presented for a high-order multi-bit ΣΔ ADC which does not require a precision multi-bit DAC in the feedback loop. Local digital level control is employed to extend integrator output dynamic range. A prototype fourth-order modulator is simulated with circuit non-idealities, showing an SNR of ~110 dB.

Single-loop delta-sigma modulator with swing suppression

In the Letter a single-loop higher-order delta-sigma modulator with a new loop topology is presented. The loop-filter is composed of both feedback and feedforward paths. No active summing element is required in the modulator implementation. The modulator has low integrator output swings and a high input dynamic range, resulting in relaxed op-amp requirements even for low-voltage operation. Simulation results of a fourth-order modulator having the proposed loop filter are also given.

Fourth-order SI delta-sigma modulators for high-frequency applications

The Letter presents a fourth-order delta-sigma modulator structure for switched-current implementation. By using 3.3 V switched-current and two-step switched-current memory cells that can be clocked at a frequency over 100 MHz, two modulators have been designed and implemented. Measurement results are also presented.

Analysis of ΔΣ modulators with zero mean stochastic inputs

In this paper, a new framework for the analysis of /spl Delta//spl Sigma/ modulators with stochastic inputs is proposed. The framework is based on assuming that the input to the one-hit quantizer is a Gaussian random process with zero mean and is thus able to interrelate the autocorrelation and cross-correlation of different signals of the modulator. Two main equations describing the behavior of two different /spl Delta//spl Sigma/ topologies are derived. These two equations are generally nonlinear and can be of arbitrary order, hence approximations are used to study some interesting cases. First, the nonlinear equations are linearized and solved analytically for first-order modulator with white inputs and numerically for colored inputs both with and without dithering. Also, a numerical iterative approach is used for second and fourth order modulators with white and colored inputs. In these cases, the variance of the one-bit quantizer input is found as a function of modulator input power. Next, the variance of the one-bit quantizer input is calculated when large amplitude oscillations are present assuming a large amplitude limit cycle to have a sinusoidal autocorrelation. Finally, an attempt is made to estimate the modulator's critical input power level beyond which these large amplitude limit cycles start. >