Fourth-order Bandpass Delta-sigma Modulator Research Articles

A Low-Distortion Fourth-Order Bandpass Sigma-Delta Modulator Using Double-Sampling Technique

In this paper, a low-distortion fourth-order bandpass sigma-delta (ΣΔ) modulator is proposed based on a switched-capacitor resonator which employs double-sampling technique to relax the requirements for circuits and reduce opamp power consumption and chip area. The modulator is based on the low-distortion low pass ΣΔ modulator. The system level simulation results compare between the low-distortion architecture and the traditional one is given. The full differential circuit applying two-path technique is implemented with TSMC0.18µm CMOS process. It achieves a peak SNR (signal-to-noise ratio) of 85.9dB and DR (dynamic range) of 91dB with 200 kHz bandwidth centered at 20MHz which are better than the conventional bandpass ΣΔ modulator.

Electromechanical-Filter-Based Bandpass Sigma–Delta Modulator

This brief proposes an electromechanical-filter-based continuous-time (CT) bandpass (BP) sigma-delta modulator for wideband digitization at high intermediate frequency (> 70 MHz). Both the mechanically coupled microelectromechanical system and the longitudinally coupled surface acoustic wave (SAW) filters can be employed as loop filters. The advantages of the electromechanical filter are its low power consumption and accurate center frequency without the need for tuning. As a proof of concept, a fourth-order BP sigma-delta modulator is demonstrated with a 110-MHz SAW filter. Realized in a 0.35- mum SiGe heterojunction-bipolar-transistor bipolar complimentary metal-oxide-semiconductor technology, the prototype chip is clocked at 440 MHz and achieves 65-dB DR and 60-dB SNDR over 1 MHz, as well as 58-dB DR and 53-dB SNDR over the 3.84-MHz signal band. The total power consumption is 57 mW under a 3-V supply.

A 1-V 10.7-MHz fourth-order bandpass /spl Delta//spl Sigma/ modulators using two switched op amps

A 1-V 10.7-MHz fourth-order bandpass delta-sigma modulator using two switched opamps (SOPs) is presented. The 3/4 sampling frequency and the double-sampling techniques are adapted for this modulator to relax the required clocking rate. The presented modulator can not only reduce the number of SOPs, but also the number of capacitors. It has been implemented in 0.25-/spl mu/m 1P5M CMOS process with MIM capacitors. The modulator can receive 10.7-MHz IF signals by using a clock frequency of 7.13 MHz. A dynamic range of 62 dB within bandwidth of 200 kHz is achieved and the power consumption of 8.45 mW is measured at 1-V supply voltage. The image tone can be suppressed by 44 dB with respect to the carrier. The in-band third-order intermodulation (IM3) distortion is -65 dBc below the desired signal.

A Sub-1V Fourth-Order Bandpass Delta-Sigma Modulator

A sub-1V fourth-order bandpass delta-sigma modulator is presented in this paper. Using the switched opamp technique enables the modulator to operate at only 0.8 V supply voltage without using volta...

On the design of a fourth-order continuous-time LC delta-sigma modulator for UHF A/D conversion

We consider the design and test of a fourth-order bandpass delta-sigma modulator (/spl Delta//spl Sigma/M) for conversion of UHF analog signals to the digital domain for heterodyning and processing there. A prototype modulator in 0.5-/spl mu/m SiGe presented in the second part of the paper achieved 40 dB of dynamic range in a 20-MHz bandwidth centered at 1 GHz and consumed 450 mW from a single 5-V supply. At the time this modulator was designed, no explicit design procedure to achieve a certain modulator performance level had been established. The first part of this paper, therefore, is devoted to explaining the tradeoffs involved in choosing the parameters for a gigahertz-clocking transconductor/LC-based /spl Delta//spl Sigma/M and formulating such an explicit design procedure. Finally, we elucidate some further design considerations, redesign the prototype to improve its simulated performance, and discuss the general appropriateness of high-speed continuous-time /spl Delta//spl Sigma/M for UHF analog-to-digital conversion.

A band-pass delta-sigma modulator for ultrasound imaging at 160 MHz clock rate

A fourth-order band-pass delta-sigma modulator for ultrasound imaging is described. It is implemented in a 0.8-/spl mu/m BiCMOS process using switched capacitors. The signal band is centered at 5 MHz and is 2.5 MHz wide, where the modulator's dynamic range is 84 dB at a sampling rate of 160 MHz. Noise shaping can be programmed between band-reject and notch functions for B-mode (wide band) and CW-mode (narrow band) scanning, respectively.

A fourth-order bandpass delta-sigma modulator with reduced numbers of op amps

A switched-capacitor quadrature demodulation technique, which is insensitive to first-order errors resulting from 90/spl deg/ phase inaccuracy and path mismatch, is demonstrated to shift a band-pass spectrum directly to dc. A sampling rate of four times the passband center frequency facilitates the quadrature demodulation and removes the 90/spl deg/ phase error. Furthermore, the path-mismatch error is canceled using the same signal path repeatedly, thereby reducing the number of op amps. A fourth-order band-pass /spl Delta/-/spl Sigma/ modulator, integrated in an area of 1 mm/sup 2/ using 2-/spl mu/m CMOS, consumes 0.8 mW with a single 3.3-V supply and exhibits an SNR of 56 dB within a 30-kHz bandwidth.

A digital FM demodulator for FM, TV, and wireless

An FM demodulator is implemented digitally in software using a quadri-correlator algorithm so that the FM function can be made compatible with future digital wireless and FM receiver systems. The proposed digital FM demodulator uses a sinc/sup 3/ decimation filter with its first zero either on the alternate channels or on the adjacent channels for high channel selectivity, a digital differentiator using a three-point approximation for frequency discrimination, and a digital division for AM rejection. A bitstream FM signal from a fourth-order bandpass delta-sigma modulator is FM-demodulated to exhibit a SNDR of 71 dB, a THD of 0.010%, and an AM rejection of 77 dB in simulations using a signal bandlimited to /sup 1///sub 200/ of the sampling frequency and amplitude-modulated with a modulation index of 0.9 (90% AM).