Four-phase Logic Research Articles

Novel dynamic CMOS logic free from problems of charge sharing and clock skew

A novel four-phase dynamic CMOS logic is proposed, analysed and chip-tested. There are two circuit configurations in the new dynamic logic. One of these can completely get rid of the problems of charge sharing and clock skew, which are inherent in most of the dynamic circuits. The other, although it can only prevent the charge sharing problem, has a larger tolerance of the clock skew than the conventional four-phase precharge-discharge logic. The second configuration is more flexible in logic design than the first configuration. Both configurations use only three clock phases to form the four-phase dynamic circuits. After a brief analysis of the clock skew problem of the conventional four-phase logic, the new dynamic logic is introduced and the two circuit configurations are described. Then, the basic analysis on the device size design and performance evaluations of the new logic are given. A serial full adder was designed and implemented by a 3.5 /jm p-well CMOS process and the experimental results obtai...

Single-chip per channel codec with filters utilizing Δ-Σ modulation

A single-chip per channel codec with filters, fabricated using a single poly-Si NMOS technology, is discussed. In the encoder, the analog signal is converted to a 2.048 M samples/s digital signal by a /spl Delta/-/spl Sigma/ modulator. Filtering necessary for the sampling rate 8 k sample/s and compression by the /spl mu/255 law are performed digitally. In the decoder, the 8 k samples/s PCM is successively resampled and converted into the 2.048 M samples/s /spl Delta/-/spl Sigma/ signal, which is then decoded by a /spl Delta/-/spl Sigma/ demodulator. All the high-frequency images, which appear around multiples of 8 kHz, are removed by digital filters. The chip has continuous-signal antialiasing and smoothing filters for the 2.048 Samples/s sampling rate. It also has reference voltage generators for /spl Delta/-/spl Sigma/ modulation/demodulation. Some of the observed characteristics are given. The NMOS /spl Delta/-/spl Sigma/ modulator requires only two on-chip matched capacitors as precision components, and does not require a linear amplifier. A deliberate quantization step imbalance is introduced to allow a low sampling rate. The main band limiting for the 8 k samples/s is done by the recursive filter. This is realized with the serial-parallel pipeline multiplier (SPPM) in four-phase logic. The whole system is integrated on a 296 mil/spl times/342 mil chip.

Four-phase logic circuits using integrated MOS transistors : R. J. Hatt, A. E. Jackets and D. B. Jarvis. Mullard Tech. Commun. No. 99, May (1969), p. 266

Four-phase logic circuits using integrated MOS transistors : R. J. Hatt, A. E. Jackets and D. B. Jarvis. Mullard Tech. Commun. No. 99, May (1969), p. 266