Forward Substrate Bias Research Articles

Low Noise Amplifier Design for IoT Wireless Communication Systems

In the era of Internet of Things (IoT), the Internet has evolved from a simple Internet function of web information access to intelligent functions of identification, position, monitoring, and management of things. Devices in the IoT must transmit data between the devices and equipment connecting to cloud. As a fog computing architecture is established proximally at the local ends of the IoT, the data transmission volume and transmission delay can be effectively reduced. IoT wireless communication is one of the essential items for complete data transmission between the devices and on-line equipment. This paper proposes the low noise amplifier (LNA) design that can be applied to the RF front-end receiver of a 2.45-GHz wireless communication system for IoT applications. The LNA is required to have characteristics of low noise factor and high signal gain in order to amplify weak signals received by the antenna. In this study, the design of 2.45-GHz LNA adopts an architecture of power-constrained simultaneous noise and input matching on the basis of the 0.18-μm CMOS process technology in order to achieve simultaneous noise and input matching at low power conditions. Both the architectures of push-pull and forward substrate bias are also utilized. The LNA demonstrates the characteristics of low noise factor, high gain, and good 1-dB gain compression. The LNA shows good potential for IoT wireless communication system applications.

Reduction of RTS Noise in Small-Area MOSFETs Under Switched Bias Conditions and Forward Substrate Bias

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> Low-frequency noise in small-area MOSFETs is dominated by random telegraph signal noise associated to the capture and emission of charge carriers by a single trap located in the gate dielectric. RTS noise degrades the performance of analog, digital, and memory circuits. In this paper, we present measurements and simulations of RTS noise in small-area MOSFETs under constant bias and switched gate bias conditions in order to investigate the impact of substrate bias on RTS noise. Our results show that a strong reduction of RTS noise under switching bias conditions is obtained when a forward substrate bias is applied during the device <emphasis emphasistype="smcaps"> off</emphasis>-state. Measurement of RTS mean emission and capture times proves that such a reduction of RTS noise is caused by a significant decrease in emission time constant occurring when a low gate voltage and a positive substrate voltage are simultaneously applied in the frame of a switching bias scheme. </para>

Noise Reduction in CMOS Circuits Through Switched Gate and Forward Substrate Bias

A new concept of noise reduction in CMOS circuits is presented taking advantage of a strong reduction of MOSFET low-frequency noise occurring under switched gate bias conditions and forward substrate bias. The effect of forward substrate bias on noise reduction is significantly larger in switched compared to constant gate bias conditions. Experimental results reveal that forward substrate bias is most effective when applied during the off-state of the transistor. A bias scheme adopting forward substrate bias only during the transistor off-state is suggested by the measurement results of transconductance efficiency gm/Id and intrinsic voltage gain gm/gds showing that these figures of merit are degraded when a forward substrate bias is applied during the on-state. As a first example exploiting the found noise reduction on circuit level, a 14 GHz pMOS VCO is presented. Our results show a significant reduction of close to carrier phase noise when a forward substrate bias is applied to the MOSFETs providing the negative conductance stage for the oscillation of the VCO. The outlined principles can be extended to other circuits and motivate new topologies and biasing schemes for analog and radio frequency CMOS circuits.

Impact of Forward Substrate Bias on Threshold Voltage Fluctuation in Metal–Oxide–Semiconductor Field-Effect Transistors

The effect of forward substrate (body) bias on threshold voltage (Vth) fluctuation in metal–oxide–semiconductor field-effect transistors (MOSFET) and its device parameter [e.g., gate length, substrate impurity concentration, gate oxide thickness (effective oxide thickness), etc.] dependence are investigated using a charge-sharing model. It is predicted that, through the application of a forward substrate bias of 0.5 V, Vth fluctuation is suppressed by up to 20% and the device parameter sensitivity of Vth is reduced in sub-100-nm devices. An experimental result demonstrating the effect of forward substrate bias on Vth fluctuation suppression is also presented.

Auger recombination-enhanced hot carrier degradation in nMOSFETs with a forward substrate bias

Enhanced hot carrier degradation in nMOSFETs with a forward substrate bias is observed. The degradation cannot be explained by conventional channel hot electron effects. Instead, an Auger recombination-assisted hot electron process is proposed. In the process, holes are injected from the forward-biased substrate and provide for Auger recombination with electrons in the channel, thus substantially increasing channel hot electron energy. Measured hot electron gate current and the light emission spectrum provide evidence that the high-energy tail of channel electrons is increased with a positive substrate bias. The drain current degradation is about ten times more serious in forward-biased substrate mode than in standard mode. The Auger-enhanced degradation exhibits positive temperature dependence and may appear to be a severe reliability issue in high temperature operation condition.

A Fast ALU Design in CMOS for Low Voltage Operation

A high‐speed 4‐bit ALU has been designed for 1 V operation to demonstrate the usefulness of the back‐gate forward substrate bias (BGFSB) method in 1.2 μm N‐well CMOS technology. The 4‐bit ALU employs a ripple carry adder and is capable of performing eight operations ‐ four arithmetic and four logical operations. The BGFSB voltage has been limited to |0.4| V. Delay time measurements are taken for all operations from the SPICE simulations with and without the back‐gate forward substrate bias. A speed advantage of a factor of about 2–2.5 is obtained with BGFSB over the conventional design.

New programming and erasing schemes for p-channel flash memory

In this work, a new programming scheme using a forward substrate bias during BBHE injection and a two-step erasing scheme has been suggested to improve the performances of p-channel flash memory. It has been found that applying a forward substrate bias increases the electron injection efficiency and improves the cell's endurance characteristics. The two-step erasing scheme, where a channel erase cycle is added after the source erase operation, is found to reduce the gate current degradation and also to improve the cell's endurance characteristics.