Forward Error Correction Decoder Research Articles

Benefits of flexibility in current and future IM-DD based TDM-PON [Invited

Due to continuously emerging high bandwidth applications, research and standardization of time division multiplexed passive optical networks (TDM-PONs) have focused on increasing the peak bitrate. However, increasing the bitrate while supporting the stringent optical power budget of a PON becomes increasingly challenging because of the larger chromatic dispersion penalties as well as reduced receiver sensitivity when the bitrate of the intensity modulation with direct-detection (IM-DD) based PON is increased. Also, increasing bitrate generally causes higher power consumption, which leads to more challenging thermal designs and misalignment with environmental targets. In this paper we give an overview of flexible concepts that can help achieve the required optical power budget and support reduced power consumption of a future IM-DD based TDM-PON. We demonstrate that a flexible PON can provide an increased overall throughput or an extended reach and power budget with the use of flexible modulation formats, probabilistic and geometric shaping, and flexible rate forward error correction (FEC). Another dimension of flexibility in the form of a configurable optical distribution network (ODN) is described and its merits and challenges are discussed. Flexible concepts based on interleaving of FEC codewords can align signal processing like FEC decoding and the protocol processing closer to the user-rate of an optical network unit (ONU), which leads to reduced power consumption. Flexibility based on multiple channels based on wavelength multiplexing or spatial multiplexing enables optimization of the power consumption to the amount of traffic on the PON. Several flexible concepts have already been adopted in the PON standards. We highlight flexible gain FEC for upstream 50G PON, the transmitter dispersion eye closure (TDEC) metric, and the flexible split-ratio ODN for power saving. Flexible modulation has not been adopted yet in PON standards, but it is expected that flexibility is more and more needed to support the performance, cost effectiveness, and power conservation of future optical access systems.

High-Throughput Polar Code Decoders with Information Bottleneck Quantization.

In digital baseband processing, the forward error correction (FEC) unit belongs to the most demanding components in terms of computational complexity and power consumption. Hence, efficient implementation of FEC decoders is crucial for next-generation mobile broadband standards and an ongoing research topic. Quantization has a significant impact on the decoder area, power consumption and throughput. Thus, lower bit widths are preferred for efficient implementations but degrade the error correction capability. To address this issue, a non-uniform quantization based on the Information Bottleneck (IB) method is proposed that enables a low bit width while maintaining the essential information. Many investigations on the use of the IB method for Low-density parity-check code) LDPC decoders exist and have shown its advantages from an implementation perspective. However, for polar code decoder implementations, there exists only one publication that is not based on the state-of-the-art Fast Simplified Successive-Cancellation (Fast-SSC) decoding algorithm, and only synthesis implementation results without energy estimation are shown. In contrast, our paper presents several optimized Fast-SSC polar code decoder implementations using IB-based quantization with placement and routing results using advanced 12 nm FinFET technology. Gains of up to 16% in area and 13% in energy efficiency are achieved with IB-based quantization at a Frame Error Rate (FER) of 10-7 and a polar code of N=1024,R=0.5 compared to state-of-the-art decoders.

Collaborative FFE-assisted simplified soft-output MLSE with LDPC for high-speed IM-DD transmissions.

In this paper, we propose a feed-forward equalizer (FFE)-assisted simplified soft-output MLSE (sMLSE) by collaborating the maximum likelihood sequence estimation (MLSE) with soft-decision low-density-parity-check (LDPC) decoding. The simplified sMLSE results in undetermined log-likelihood ratio (LLR) magnitudes when the reserved level is less than or equal to the half of modulation order. This severely degrades the performance of soft-decision forward error correction (SD-FEC) decoding. In the FFE-assisted simplified sMLSE, we use the LLRs calculated from pre-set FFE to replace these undetermined LLRs of simplified sMLSE. Thus, the proposed method eliminates the SD-FEC decoding performance degradation resulted from simplification. We conduct experiments to transmit 184-Gb/s PAM-4 or 255-Gb/s PAM-8 signal in IM-DD system at C-band to evaluate the performance of the proposed sMLSE. The results show that the proposed sMLSE can effectively compensate for the degradation of LLR quality. For 255-Gb/s PAM-8 signal transmissions, the FFE-assisted simplified sMLSE achieves almost the same SD-FEC decoding performance as the conventional sMLSE but with 85% complexity reduction.

S-Band WDM Transmission Using PPLN-Based Wavelength Converters and 400-Gb/s C-Band Real-Time Transceivers

Multi-band WDM transmission beyond the C+L-band is a promising technology for achieving larger capacity transmission by a limited number of installed fibers. In addition to the C- and L-band, we can expect use the S-band as the next band. Although the development of optical components for new bands, particularly transceivers, entails resource dispersion, which is one of the barriers to the realization of multi-band systems, wavelength conversion by transparent all-optical signal processing enables new wavelength band transmission using existing components. Therefore, we proposed a transmission system including a new wavelength band such as the S-band and made it possible to use a transceiver for the existing band by performing the whole-band wavelength conversion without using a transceiver for the new band. As a preliminary verification to demonstrate multi-band WDM transmission including S-band, we investigated the application of a novel wavelength converter between C-band and S-band, which consists of periodically poled lithium niobate waveguide, to the proposed system. We first characterized the conversion efficiency and noise figure of the wavelength converter and estimated the transmission performance of the system through the wavelength converter. Using the evaluated wavelength converters and test signals of 64 channels arranged in the C-band at 75-GHz intervals, we constructed an experimental setup for S-band transmission through an 80-km standard single-mode fiber. We then demonstrated error-free transmission of real-time 400-Gb/s DP-16QAM signals after forward error correction decoding. From the experimental results, it was clarified that thewavelength converter which realizes the uniformlossless conversion covering the whole C-band effectively achieves the S-band WDM transmission, and it was verified that the capacity improvement of the multi-band WDM system including the S-band can be expected by applying it in combination with the C+L-band WDM system.

Accelerating the Verification of Forward Error Correction Decoders by PCIe FPGA Cards

Pre-silicon forward error correction (FEC) decoding hardware is typically designed using hardware description languages (HDL). Its verification is a hard task due to its intrinsic tendency to correct errors. The generation and injection of millions of random inputs as well as the cross-checking of the corresponding outputs is highly recommended. Using HDL simulations for such work leads to prohibitive execution times. This letter proposes a verification strategy in which the software testbed is executed on a multi-core host and the hardware under verification is prototyped on a PCIe accelerator card. Data are transferred in big blocks of codewords over a high-bandwidth PCIe channel and applied to the decoder using a pipeline management to maximize the use of computational resources and to minimize the verification time. The decoder is replicated with parallel access to DDRs. OpenMP is used to leverage the parallel capabilities of the host and OpenCL, together with Xilinx Runtime Library (XRT), to manage the PCIe FPGA card execution. The results show an important speed-up with respect to HDL simulation and to other prototyping approaches.

Real-Time FPGA Investigation of Interplay Between Probabilistic Shaping and Forward Error Correction

In this work, we implement a complete probabilistic amplitude shaping (PAS) architecture on a field-programmable gate array (FPGA) platform to study the interplay between probabilistic shaping (PS) and forward error correction (FEC). Due to the fully parallelized input–output interfaces based on look up table (LUT) and low computational complexity without high-precision multiplication, hierarchical distribution matching (HiDM) is chosen as the solution for real time probabilistic shaping. In terms of FEC, we select two kinds of the mainstream soft decision-forward error correction (SD-FEC) algorithms currently used in optical communication system, namely Open FEC (OFEC) and soft-decision quasi-cyclic low-density parity-check (SD-QC-LDPC) codes. Through FPGA experimental investigation, we studied the impact of probabilistic shaping on OFEC and LDPC, respectively, based on PS-16QAM under moderate shaping, and also the impact of probabilistic shaping on LDPC code based on PS-64QAM under weak/strong shaping. The FPGA experimental results show that if pre-FEC bit error rate (BER) is used as the predictor, moderate shaping induces no degradation on the OFEC performance, while strong shaping slightly degrades the error correction performance of LDPC. Nevertheless, there is no error floor when the output BER is around 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-15</sup> . However, if normalized generalized mutual information (NGMI) is selected as the predictor, the performance degradation of LDPC will become insignificant, which means pre-FEC BER may not a good predictor for LDPC in probabilistic shaping scenario. We also studied the impact of residual errors after FEC decoding on HiDM. The FPGA experimental results show that the increased BER after HiDM decoding is within 10 times compared to post-FEC BER.

Latency and Complexity Analysis of Flexible Semi-Parallel Decoding Architectures for 5G NR Polar Codes

Polar codes are one of the most recent additions to the family of forward error correction (FEC) codes, having recently been adopted in the 5G New Radio (NR) standard for the control channel. However, the stringent requirements introduced by the 5G standard in terms of block length and code rate flexibility, along with low end-to-end latency and high error correction performance represent a major challenge for their hardware implementation. In this context, we study the impact of main code and decoder design parameters on the latency, throughput, and the hardware complexity of semi-parallel decoding architectures. The impact of these parameters on the hardware efficiency of semi-parallel architectures is significant. Therefore, we propose two multi-frame decoding approaches that increase the throughput and improve the utilisation rate of the processing units of these architectures. Detailed analytical and logic synthesis results are provided and compared for a large range of values in order to constitute a reference for the implementation of flexible, yet efficient FEC decoders for polar codes.

Adaptive Turbo Equalization for Nonlinearity Compensation in WDM Systems

In this paper, the performance of adaptive turbo equalization for nonlinearity compensation (NLC) is investigated. A turbo equalization scheme is proposed where a recursive least-squares (RLS) algorithm is used as an adaptive channel estimator to track the time-varying intersymbol interference (ISI) coefficients associated with inter-channel nonlinear interference (NLI) model. The estimated channel coefficients are used by a MIMO $2\times 2$ soft-input soft-output (SISO) linear minimum mean square error (LMMSE) equalizer to compensate for the time-varying ISI. The SISO LMMSE equalizer and the SISO forward error correction (FEC) decoder exchange extrinsic information in every turbo iteration, allowing the receiver to improve the performance of the channel estimation and the equalization, achieving lower bit-error-rate (BER) values. The proposed scheme is investigated for polarization multiplexed 64QAM and 256QAM, although it applies to any proper modulation format. Extensive numerical results are presented. It is shown that the scheme allows up to 0.7 dB extra gain in effectively received signal-to-noise ratio (SNR) and up to 0.2 bits/symbol/pol in generalized mutual information (GMI), on top of the gain provided by single-channel digital backpropagation.

Performance Prediction Recipes for Optical Links

Although forward error-correction (FEC) coding is an essential part of modern fiber-optic communication systems, it is impractical to implement and evaluate FEC in transmission experiments and simulations. Therefore, it is desirable to accurately predict the end-to-end link performance including FEC from transmission data recorded without FEC. In this tutorial, we provide ready-to-implement "recipes" for such prediction techniques, which apply to arbitrary channels and require no knowledge of information or coding theory. The appropriate choice of recipe depends on properties of the FEC encoder and decoder. The covered metrics include bit error rate, symbol error rate, achievable information rate, and asymptotic information, in all cases computed using a mismatched receiver. Supplementary software implementations are available.

Compressed Shaping: Concept and FPGA Demonstration

Probabilistic shaping (PS) has been widely studied and applied to optical fiber communications. The encoder of PS expends the number of bit slots and controls the probability distribution of channel input symbols. Not only studies focused on PS but also most works on optical fiber communications have assumed source uniformity (i.e. equal probability of marks and spaces) so far. On the other hand, the source information is in general nonuniform, unless bit-scrambling or other source coding techniques to balance the bit probability is performed. Interestingly, one can exploit the source nonuniformity to reduce the entropy of the channel input symbols with the PS encoder, which leads to smaller required signal-to-noise ratio at a given input logic rate. This benefit is equivalent to a combination of data compression and PS, and thus we call this technique compressed shaping. In this work, we explain its theoretical background in detail, and verify the concept by both numerical simulation and a field programmable gate array (FPGA) implementation of such a system. In particular, we find that compressed shaping can reduce power consumption in forward error correction decoding by up to 90% in nonuniform source cases. The additional hardware resources required for compressed shaping are not significant compared with forward error correction coding, and an error insertion test is successfully demonstrated with the FPGA.

Generalized weighted bit-flipping LDPC decoding for asymmetric optical channels

Efficient low-complexity and low-latency forward error correction (FEC) decoding is vital in high-speed optical receivers. The weighted bit-flipping (WBF) decoding algorithm is a low-complexity and high-performance iterative decoder for low-density parity-check (LDPC) codes, devised for symmetric Gaussian channels. In this paper, we present a generalization of the WBF algorithm and its variants to discrete and continuous asymmetric optical channels which have signal-dependent noises. We have employed a fully analytical approach to derive the generalized WBF decoders, and show that they can achieve a net coding gain within 0.5 dB of that of the soft-decision near-optimal decoding.

Block Error Detection Driven Nonlinearity Compensation for Optical Fiber Communications

The perturbation-based nonlinearity compensation (NLC) method is considered in conjunction with a forward error correction (FEC) code that is capable of detecting block errors. The FEC decoding is performed prior to the NLC, and NLC is then performed only for blocks, that could not be decoded correctly. The total NLC complexity is thus dramatically reduced to down to 1% in some cases w.r.t. the standard, hard decision-directed NLC performed prior to the FEC decoding. Negligible FEC decoding complexity increase is required for the subsequent decoding of the nonlinearity-compensated blocks. The proposed method achieves and sometimes outperforms the standard perturbation based NLC at a fraction of the overall complexity. Polar codes are used to exemplify the method.

Implementation of an LDPC decoder for IEEE 802.11n using VivadoTM High-Level Synthesis

The increasing complexity of hardware designs calls for design methodolgies that use more abstract design entries and increased automation of the implementation process. Highlevel synthesis (HLS) has been a research topic for the past 20 years, and current tools, such as Xilinx VivadoTM HLS promise to bring HLS to widespread use. In this paper we use Xilinx VivadoTMHLS to design an LDPC decoder for 802.11n. Forward error correction decoders are typically implemented in hardware due to the high processing requirements and therefore an LDPC decoder is an appropriate example to demonstrate the power of high-level synthesis

Hard-input FEC evaluation using Markov models for equalization-induced correlated errors in 50G PON

Channel measurements for a 50G passive optical network (PON) show a significant amount of intersymbol interference (ISI) due to chromatic dispersion (CD) and the use of low-cost, bandwidth-limited 25 Gbaud class components. The channel characteristics at the input of the forward error correction (FEC) decoder are measured for several receiver equalization schemes, and the error correlation at the output of each equalizer is characterized using a sub-class of a Fritchman’s Markov model. This model is used to generate error sequences that match the observed correlation statistics, and these sequences are then used to evaluate the performance of a candidate low-density parity-check (LDPC) code with lifting factor 256 and hard-input decoding. It is shown that for a bandwidth-limited 50G PON system with 83 ps/nm dispersion, the optical power sensitivity penalty (OPSP) due to a reduction in error correction performance caused by correlated errors is 0.3–0.6 dB. Precoding, i.e., differential encoding of the input data and differential decoding, helps to reduce the OPSP for some equalizers, but the penalty increases for other equalizers. The use of a 256-bit segment-interleaver only marginally improves the decoding performance, whereas bit-interleaving across four codewords reduces the penalty to within 0.05 dB relative to the binary symmetric channel.

Variable-Rate VLSI Architecture for 400-Gb/s Hard-Decision Product Decoder

Variable-rate transceivers, which adapt to the conditions, will be central to energy-efficient communication. However, fiber-optic communication systems with high bit-rate requirements make design of flexible transceivers challenging, since additional circuits needed to orchestrate the flexibility will increase area and degrade speed. We propose a variable-rate VLSI architecture of a forward error correction (FEC) decoder based on hard-decision product codes. Variable shortening of component codes provides a mechanism by which code rate can be varied, the number of iterations offers a knob to control the coding gain, while a key-equation solver module that can swap between error-locator polynomial coefficients provides a means to change error correction capability. Our evaluations based on 28-nm netlists show that a variable-rate decoder implementation can offer a net coding gain (NCG) range of 9.96-10.38dB at a post-FEC bit-error rate of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-15</sup> . The decoder achieves throughputs in excess of 400Gb/s, latencies below 53ns, and energy efficiencies of 1.14pJ/bit or less. While the area of the variable-rate decoder is 31% larger than a decoder with a fixed rate, the power dissipation is a mere 5% higher. The variable error correction capability feature increases the NCG range further, to above 10.5dB, but at a significant area cost.

Efficient Implementation of 400 Gbps Optical Communication FEC

We focus on a hardware implementation of the concatenated forward error-correction (FEC) decoder defined in 400ZR implementation agreement to provide a throughput of 400 Gbps over fiber-optical communication links. We propose a soft-input hard-output low-complexity decoding algorithm for the inner Hamming code. We demonstrate that the algorithm leads to an efficient hardware design with low silicon area and power dissipation. We then propose a hardware implementation architecture of the outer staircase decoder. It features a highly optimized low-power implementation of Bose-Chaudhuri-Hocquenghem (BCH) component decoders and the staircase decoder memory that can be efficiently accessed by either vertical or horizontal component decoders. Finally, we analyze the hardware implementation of the entire 400ZR decoder and investigate the trade-off in terms of power, area, and speed, that results from the inner/outer decoder concatenation and is dictated by the bit-error rate at the output of the inner decoder.

Post-FEC BER Benchmarking for Bit-Interleaved Coded Modulation With Probabilistic Shaping

Accurate performance benchmarking after forward error correction (FEC) decoding is essential for system design in optical fiber communications. Generalized mutual information (GMI) has been shown to be successful at benchmarking the bit-error rate (BER) after FEC decoding (post-FEC BER) for systems with soft-decision (SD) FEC without probabilistic shaping (PS). However, GMI is not relevant to benchmark post-FEC BER for systems with SD-FEC and PS. For such systems, normalized GMI (NGMI), asymmetric information (ASI), and achievable FEC rate have been proposed instead. They are good at benchmarking post-FEC BER or to give an FEC limit in bit-interleaved coded modulation (BICM) with PS, but their relation has not been clearly explained so far. In this paper, we define generalized L-values under mismatched decoding, which are connected to the GMI and ASI. We then show that NGMI, ASI, and achievable FEC rate are theoretically equal under matched decoding but not under mismatched decoding. We also examine BER before FEC decoding (pre-FEC BER) and ASI over Gaussian and nonlinear fiber-optic channels with approximately matched decoding. ASI always shows better correlation with post-FEC BER than pre-FEC BER for BICM with PS. On the other hand, post-FEC BER can differ at a given ASI when we change the bit mapping, which describes how each bit in a codeword is assigned to a bit tributary.

30% Reach Increase via Low-Complexity Hybrid HD/SD FEC and Improved 4D Modulation

Current optical coherent transponders technology is driving data rates towards 1 Tb/s/{\lambda}and beyond. This trend requires both high-performance coded modulation schemes and efficient implementation of the forward-error-correction (FEC) decoder. A possible solution to this problem is combining advanced multidimensional modulation formats with low-complexity hybrid HD/SD FEC decoders. Following this rationale, in this paper we combine two recently introduced coded modulation techniques:the geometrically-shaped 4D-64 polarization ring-switched and the soft-aided bit-marking-scaled reliability decoder. This joint scheme enabled us to experimentally demonstrate the transmission of 11x218 Gbit/s channels over transatlantic distances at 5.2bit/4D-sym. Furthermore, a 30% reach increase is demonstrated over PM-8QAM and conventional HD-FEC decoding for product codes.

Performance Monitoring for Live Systems with Soft FEC and Multilevel Modulation

Performance monitoring is an essential function for margin measurements in live systems. Historically, system budgets have been described by the Q-factor converted from the bit error rate (BER) under binary modulation and direct detection. The introduction of hard-decision forward error correction (FEC) did not change this. In recent years technologies have changed significantly to comprise coherent detection, multilevel modulation and soft FEC. In such advanced systems, different metrics such as (nomalized) generalized mutual information (GMI/NGMI) and asymmetric information (ASI) are regarded as being more reliable. On the other hand, Q budgets are still useful because pre-FEC BER monitoring is established in industry for live system monitoring. The pre-FEC BER is easily estimated from available information of the number of flipped bits in the FEC decoding, which does not require knowledge of the transmitted bits that are unknown in live systems. Therefore, the use of metrics like GMI/NGMI/ASI for performance monitoring has not been possible in live systems. However, in this work we propose a blind soft-performance estimation method. Based on a histogram of log-likelihood-values without the knowledge of the transmitted bits, we show how the ASI can be estimated. We examined the proposed method experimentally for 16 and 64-ary quadrature amplitude modulation (QAM) and probabilistically shaped 16, 64, and 256-QAM in recirculating loop experiments. We see a relative error of 3.6%, which corresponds to around 0.5 dB signal-to-noise ratio difference for binary modulation, in the regime where the ASI is larger than the assumed FEC threshold. For this proposed method, the digital signal processing circuitry requires only a minimal additional function of storing the L-value histograms before the soft-decision FEC decoder.

An Adaptive BLAST Successive Interference Cancellation Method for High Data Rate Perfect Space-Time Coded MIMO Systems

Linear dispersion (LD) based perfect space-time codes (STBCs) are an efficient means of increasing a multiple-input multiple-output (MIMO) system's overall diversity gain while maintaining the same spectral efficiency as a traditional spatial multiplexed (SM) MIMO system. Because the decoding procedure of LD codes traditionally requires the entire code to be received and decoded simultaneously, complexity increases proportional to the square of the MIMO array size. In this paper, we leverage the increased number of spatial and temporal layers at the decoder to dynamically reduce the complexity of a BLAST optimum ordering and successive interference cancellation (SIC) detector based on the instantaneous system capacity and data rate. The novel approach proposed in this paper is channel code and modulation agnostic, meaning the underlying constellation can be HEX or QAM and there is no feedback from a forward error correction (FEC) decoder, which makes the design useful in a wide range of MIMO systems employing LD codes with linear detectors. We investigate the method's bit error rate (BER) using MIMO dimensions up to $8 \times 8$ and bits per channel use (BPCU) up to 32. We analyze the system's run-time complexity and BER performance in software and implement perfect coding along with the novel method presented here in a custom MIMO orthogonal frequency division multiplexing (OFDM) system and test it over-the-air using an Ettus Research X310 software-defined radio (SDR) testbed.