Forward Discrete Wavelet Research Articles

Memory Efficient Hardware Architecture for 5/3 Lifting-Based 2-D Forward Discrete Wavelet Transform

Novel memory efficient hardware architecture for 5/3 lifting-based two-dimensional (2-D) forward discrete wavelet transform (DWT) is presented in this paper. The proposed novel architecture requires total memory of size less than 4N in case of J levels of decomposition for an N×N image, which is the lowest size of required total memory compared with the best of the existing state-of-the-art solutions. This novel architecture is able to process multiple levels of decomposition simultaneously by using only one one-dimensional (1-D) 5/3 lifting-based horizontal filter and one 1-D 5/3 lifting-based vertical filter. Since 5/3 DWT filter is the default filter for reversible transformation in JPEG 2000 standard, the proposed hardware architecture is quite suitable for the implementation in a JPEG 2000 coder.

Novel one-dimensional and two-dimensional forward discrete wavelet transform 5/3 filter architectures for efficient hardware implementation

We implemented a more efficient circuit for one-dimensional (1-D) forward discrete wavelet transform (DWT) 5/3 filter. Our design utilizes processing and memory resources that are wasted in some other state-of-the-art solutions and is at least 33% simpler in terms of used registers, is 17% simpler in terms of used logic elements, has 7% higher maximum operating frequency and has 2% lower total power dissipation than previously published designs. The advantages of our design are achieved by a novel non-stationary filter topology which reuses the same registers for generating both low-pass and high-pass output coefficients, in different time slots, due to feed-forward and feedback paths. Our design is suitable for image compression systems which use 5/3 filter, e.g., JPEG 2000. We also proposed two-dimensional (2-D) DWT 5/3 architecture which uses implemented 1-D DWT filter design. The proposed 2-D DWT architecture outperforms all previously published architectures in terms of required memory capacity, which is at least 20% lower than memory capacity in any other reported solution.

Efficient parallel architecture for multi-level forward discrete wavelet transform processors

A resource efficient and high-performance architecture for a two-dimensional multi-level discrete wavelet transform processor is presented in this paper. The JPEG2000 standard integer lossless 5–3 filter has been implemented. It achieves optimal hardware utilisation with minimal combinational logic block slices and high frequency of operation. To reduce the hardware complexity and to achieve high performance the proposed architecture implements lifting scheme with a single multiplier-free processing element to perform both predict and update operations. Symmetric extension is used at image boundaries without requiring any extra clock cycle. The generic architecture is very flexible and can perform up to five levels of forward transform on any arbitrary image size. Synthesis of the 5-level architecture on Xilinx Virtex 5 FPGA shows that the processor can achieve a maximum frequency of operation of 221.44MHz. The reduced hardware complexity and high frequency of operation render the design suitable for incorporation in image processing applications requiring fast operations. The 5-level design has been successfully implemented on a Xilinx Spartan 3E FPGA, utilising only 1104 slices for a 512-by-512 pixel test image, the lowest hardware requirements for a 5-level discrete wavelet transform processor reported to date.

Removal of ECG interference from surface respiratory electromyography

The signal to noise ratio (SNR) of surface respiratory electromyography signal is very low. Indeed EMG signal is contaminated by different types of noise especially the cardiac artefact ECG. This article explores the problem of removing ECG artefact from respiratory EMG signal. The new method uses an adaptive structure with an electrocardyographic ECG reference signal carried out by wavelet decomposition. The proposed algorithm requires only one channel to both estimating the adaptive filter input reference noise and the respiratory EMG signal. This new technique demonstrates how two steps will be combined: the first step decomposes the signal with forward discrete wavelet transform into sub-bands to get the wavelet coefficients. Then, an improved soft thresholding function was applied. And the ECG input reference signal is reconstructed with the transformed coefficients whereas, the second uses an adaptive filter especially the LMS one to remove the ECG signal. After trying statistical as well as mathematical analysis, the complete investigation ensures that all details and steps make proof that our rigorous method is appropriate. Compared to the results obtained using previous techniques, the results achieved using the new algorithm show a significant improvement in the efficiency of the ECG rejection.

A note on "Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet Transform"

A flipping structure for the discrete wavelet transform (DWT) was proposed by Huang et al., which aimed at shortening the critical path of the lifting-based one-dimensional (1-D) architecture and reducing the number of pipeline register used in 1-D architecture as well as the size of temporal buffer (TB) required in the line-based two-dimensional (2-D) architecture. In this paper, we explore the intrinsic relationship between the size of TB required in the line-based architecture for 2-D DWT (LBA2DDWT) and the number of registers used in a 1-D DWT module, and present a modified view on this issue that has been proposed by Huang et al. An improved method of mapping the registers used in 1-D DWT architecture to the TB required in LBA2DDWT is presented, which reduces more efficiently the size of memory required in LBA2DDWT than Huang's method. A parallel-based lifting scheme (PLS) for DWT and its VLSI architecture are presented. The proposed PLS of DWT not only reduces efficiently the critical path but also results in the equality of the forward discrete wavelet transform and inverse discrete wavelet transform implementations. Compared with Huang's method, the proposed PLS is more efficient in reducing critical path and/or the number of registers of VLSI implementation for 1-D DWT, and it can be concluded that the flipping structure of DWT is a special case of the PLS-based implementation.

VLSI Architecture for Forward Discrete Wavelet Transform Based on B-spline Factorization

Based on B-spline factorization, a new category of architectures for Discrete Wavelet Transform (DWT) is proposed in this paper. The B-spline factorization mainly consists of the B-spline part and the distributed part. The former is proposed to be constructed by use of the direct implementation or Pascal implementation. And the latter is the part introducing multipliers and can be implemented with the Type-I or Type-II polyphase decomposition. Since the degree of the distributed part is usually designed as small as possible, the proposed architectures could use fewer multipliers than previous arts, but more adders would be required. However, many adders can be implemented with smaller area and lower speed because only few adders are on the critical path. Three case studies, including the JPEG2000 default (9, 7) filter, the (6, 10) filter, and the (10, 18) filter, are given to demonstrate the efficiency of the proposed architectures.

A high-throughput, memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000

In this paper, the design and implementation of an optimized hardware architecture in terms of speed and memory requirements for computing the tile-based 2D forward discrete wavelet transform for the JPEG2000 image compression standard, are described. The proposed architecture is based on a well-known architecture template for calculating the 2D forward discrete wavelet transform. This architecture is derived by replacing the filtering units by our previously published throughput-optimized ones and by developing a scheduling algorithm suited to the special features of our filtering units. The architecture exhibits high-performance characteristics due to the throughput-optimized filters. Also, the extra clock cycles required due to the tile-based version of the discrete wavelet transform are partially compensated by the proper scheduling of the filters. The developed scheduling algorithm results in reduced memory requirements compared with existing architectures.