Formal Verification Research Articles

Hybrid Algorithm Selection and Hyperparameter Tuning on Distribute Machine Learning Resources: Hierarchical Agent-based Approach

Algorithm selection and hyperparameter tuning are critical steps in both academic and applied machine learning (ML). These steps are becoming increasingly delicate due to the extensive rise in the number, diversity, and distributed nature of ML resources. Multi-agent systems, when applied to the design of ML platforms, bring about several distinctive characteristics, such as scalability, flexibility, and robustness, just to name a few. This article proposes a fully automatic and collaborative agent-based mechanism for selecting distributed ML algorithms and simultaneously tuning their hyperparameters. Our method builds upon an existing agent-based hierarchical ML platform and augments its query structure to support the aforementioned functionalities without being limited to specific learning, selection, and tuning mechanisms. We have conducted theoretical assessments, formal verification, and analytical study to demonstrate the correctness, resource utilization, and computational efficiency of our technique. According to the results, our solution is algorithmically correct and exhibits linear time and space complexity in relation to the size of available resources. To further verify its correctness and demonstrate its effectiveness and flexibility across a range of algorithmic options and datasets, the article also presents a series of empirical results on a system composed of 24 algorithms and 9 datasets. The findings not only highlight the efficiency and scalability of the proposed approach, but also show its flexibility and openness to responding to the dynamic and distributed ML ecosystem.

Formal Verification and Security Analysis of Go-based New Simple Queue System

Formal Verification and Security Analysis of Go-based New Simple Queue System

Timed Interpreted Systems as a New Agent-Based Formalism for Verification of Timed Security Protocols

This article introduces a new method for modelling and verifying the execution of timed security protocols (TSPs) and their time-dependent security properties. The method, which is novel and reliable, uses an extension of interpreted systems, accessible semantics in multi-agent systems, and timed interpreted systems (TISs) with dense time semantics to model TSP executions. We enhance the models of TSPs by incorporating delays and varying lifetimes to capture real-life aspects of protocol executions. To illustrate the method, we model a timed version of the Needham–Schroeder Public Key Authentication Protocol. We have also developed a new bounded model checking reachability algorithm for the proposed structures, based on Satisfiability Modulo Theories (SMTs), and implemented it within the tool. The method comprises a new procedure for modelling TSP executions, translating TSPs into TISs, and translating TISs’ reachability problem into the SMT problem. The paper also includes thorough experimental results for nine protocols modelled by TISs and discusses the findings in detail.

Towards a Verifiable Toolchain for Robotics

There is a growing need for autonomous robots to complete complex tasks robustly in dynamic and unstructured environments. However, current robot performance is limited to simple tasks in controlled environments. To improve robot autonomy in complex environments, the robot's deliberation system must be able to synthesise correct plans for a task and generate contingency plans for handling anomalous scenarios that were not expected at design time. The robustness of such a system can be quantified using techniques for formal verification and validation. This paper outlines the progress of EU project CONVINCE (CONtext-aware Verifiable and adaptIve dyNamiC dEliberation), which aims to develop a software toolchain that aids developers in designing, developing, and deploying robot deliberation systems that are fully verified. We describe our modelling approach, each of the toolchain components, and how they interact. We also discuss survey results which demonstrate the demand for a verifiable toolchain among the robotics community.

EnR: extend and reduce methodology to enable formal verification of truncated adders

Abstract Truncated adders are widely used in applications where using lower bit-width is enough to generate the desired outputs. Truncated adders give benefits in area, power, and delay as compared to their non-truncated counterparts. While prior works deal with the formal verification of n-bit adders, there is no prior work dealing with the formal verification of unverified m-bit truncated adders using verified n-bit adder designs, where m < ${< } $ n. In this work, we propose a methodology that enables the verification for any truncated adder designs, irrespective of the architecture, called Extend and Reduce (EnR). EnR uses a three-step methodology to formally verify the truncated adders, which are considered as Design Under Verification (DUV). Firstly, it extends the bit-width of the DUV (truncated adder) to match with the nearest higher 2 n -bit adder, called an Extended Truncated Adder (ETA). Secondly, it reduces off-the-shelf formally verified golden reference adder design by forcing 0’s at the input bits to match it to the extended DUV design and re-synthesizing it to generate a Reduced Golden Adder (RGA). Lastly, a combinational equivalence check is then performed between the ETA and the RGA for formal verification. If the truncated adder is correct, the ETA and RGA are equivalent and vice versa. We evaluate a number and variety of adder designs to show the efficacy of the EnR methodology. We performed the formal verification using Binary Decision Diagrams (BDDs) and And-Inverter Graphs (AIGs). Lastly, we show the scalability of EnR methodology using adders up to a bit-width of 512 bits. ACM CCS Hardware → Arithmetic and datapath circuits; Combinational circuits; Equivalence checking; Functional verification; Electronic design automation.

Dynamics simulations of hypoxia inducible factor-1 regulatory network in cancer using formal verification techniques

Hypoxia-inducible factor-1 (HIF-1) regulates cell growth, protein translation, metabolic pathways and therefore, has been advocated as a promising biological target for the therapeutic interventions against cancer. In general, hyperactivation of HIF-1 in cancer has been associated with increases in the expression of glucose transporter type-1 (GLUT-1) thus, enhancing glucose consumption and hyperactivating metabolic pathways. The collective behavior of GLUT-1 along with previously known key players AKT, OGT, and VEGF is not fully characterized and lacks clarity of how glucose uptake through this pathway (HIF-1) probes the cancer progression. This study uses a Rene Thomas qualitative modeling framework to comprehend the signaling dynamics of HIF-1 and its interlinked proteins, including VEGF, ERK, AKT, GLUT-1, β-catenin, C-MYC, OGT, and p53 to elucidate the regulatory mechanistic of HIF-1 in cancer. Our dynamic model reveals that continuous activation of p53, β-catenin, and AKT in cyclic conditions, leads to oscillations representing homeostasis or a stable recovery state. Any deviation from this cycle results in a cancerous or pathogenic state. The model shows that overexpression of VEGF activates ERK and GLUT-1, leads to more aggressive tumor growth in a cancerous state. Moreover, it is observed that collective modulation of VEGF, ERK, and β-catenin is required for therapeutic intervention because these genes enhance the expression of GLUT-1 and play a significant role in cancer progression and angiogenesis. Additionally, SimBiology simulation unveils dynamic molecular interactions, emphasizing the need for targeted therapeutics to effectively regulate VEGF and ERK concentrations to modulate cancer cell proliferation.

Formal Verification with ABV : A Superior Alternative to UVM for Complex Computing Chips

This article explores the evolution and effectiveness of formal verification enhanced with Assertion-Based Verification (ABV) as a superior alternative to traditional Universal Verification Methodology (UVM) in complex computing chip design. Through analysis of implementation data from major semiconductor companies, including Intel's Core i7 and IBM's POWER processors, the article demonstrates how formal methods achieve up to 100% coverage of critical modules compared to UVM's typical 80-85% coverage. The research presents quantitative evidence of formal verification's advantages, including a 25-30% reduction in verification cycles, a 40% increase in security vulnerability detection, and a 55% reduction in overall verification time through advanced techniques such as compositional verification and proof decomposition. The article also addresses scalability challenges and resource optimization strategies, providing a comprehensive framework for implementing formal verification in modern chip design workflows.

Automatic construction and verification algorithm for smart contracts based on formal verification

As an emerging technology, blockchain demonstrates strong potential for applications in digital finance. As a core component of blockchain, the security and reliability of smart contracts is crucial. To ensure the high reliability of smart contracts, this study employs formal construction and verification techniques based on game theory. Initially, the profit function is defined using distortion techniques, and a game model for supply chain participation is designed. However, the equilibrium solution of the two-party game does not represent the optimal solution for the supply chain system. Therefore, the study introduces third-party participation to optimize the equilibrium solution. Finally, a probability model detection method is used to verify the constructed smart contract model. The results show that the supply chain model, analyzed through formal methods, has attributes consistent with theoretical analysis. Consequently, the research on automatic construction and verification algorithms for smart contracts based on formal verification proves to be effective and feasible in practical applications.

Model Checking Spatial Reachability Specifications of Public Transport Networks

Well-designed spatial configurations of public transport stops and routes in big cities contribute to enhancing daily travel services for citizens, effectively mitigating traffic congestion, and addressing other pertinent challenges. When examining spatial layouts of public transport networks (PTNs), various reachability demands between stops or urban Points of Interest (POIs) are crucial issues should be firstly taken into account. Existing methods to investigate spatial reachability properties of PTNs generally need to construct some evaluation functions, or survey reachability metrics through some network analysis techniques. These methods are often impractical, as the functional relations always cannot be accurately defined, or some global network metrics cannot provide explicit evidences for PTN layout planning or optimization.In this paper, we introduce spatial model checking techniques to the formal verification of the reachability specifications of PTN to guarantee the rationality of PTN layout. First, we extend closure space structure by incorporating attribute labeling functions and logical propositions for public transport stops and routes to develop a formal spatial verification model for PTN spatial layout. Second, we propose several novel reachability operators based on the logical operators of the Spatial Logic for Closure Space (SLCS) to facilitate the logical characterization of reachability specifications. Third, we perform the verification of the transformed reachability formulas by the spatial model checker topochecker. Examples demonstrate the effectiveness of our approach and indicate that it can perform automatic, descriptive and comprehensible verification of the reachability properties PTN layouts.

Ensuring the Correctness and Reliability of CBPS System Using Event‐B

ABSTRACTDuring the early phases of software system development, error detection can be challenging due to the complexity of both the requirements and the operating environments. This paper advocates for the utilization of formal modelling and verification throughout the first phases of systems development to promptly detect and correct errors. The formalism employed throughout is Event‐B, which is backed by the Rodin toolset. To conquer requirements complexity, the frameworks of set theory and first‐order logic are employed, which provide the necessary tools for formalizing and analysing the properties and behaviours associated with Event‐B. Also, we detail the way in which modelling may be used to achieve abstraction, as well as the way in which refinement can be used to manage complexity through layering. Furthermore, we emphasize the significance of model validation and verification in improving the precision of formal models and requirements in IoT communication systems. The model is exemplified using a Content‐Based Publish Subscribe System (CBPS), with a special emphasis on a fire alarm system as a motivating example.

Formal Verification of Virtualization-Based Trusted Execution Environments

Formal Verification of Virtualization-Based Trusted Execution Environments

Enhancing Translation Validation of Compiler Transformations with Large Language Models

This paper presents a framework that integrates Large Language Models (LLMs) into translation validation, targeting LLVM compiler transformations where formal verification tools fall short. Our framework utilizes the existing tools, like Alive2, to perform initial validation. For transformations deemed unsolvable by traditional methods, our approach leverages fine-tuned LLMs to predict soundness or unsoundness, with subsequent fuzzing applied to identify counterexamples for unsound transformations. Our approach has proven effective in complex scenarios, such as deep-learning accelerator designs, enhancing the reliability of compiler transformations.

Memoization in Model Checking for Safety Properties with Multi-Swarm Particle Swarm Optimization

In software engineering, errors or faults in software systems often lead to critical social problems. One effective methodology to tackle this problem is model checking, which is an automated formal verification technique. In traditional model checking, the task of finding specification errors is reduced to deterministic search techniques such as Depth-First Search. Recent research has shown that swarm intelligence offers a powerful search capability compared to traditional techniques. In particular, multi-swarm Particle Swarm Optimization is known to be efficient and can mitigate the state-space explosion problem, i.e., the exponential increase in the search space with a linear increase in the problem size. However, the state-space explosion problem is still significant when verifying very large systems. Further performance improvement is needed. To achieve this, we propose a novel memoization or cache mechanism for storing tentative solutions for reuse in the later stages of the search procedure. For each stage, a candidate solution computed by a swarm is summarized efficiently and heuristically to consolidate similar solutions into a single representative solution. We store the summary and its associated solutions in key-value maps. Instead of computing known solutions repeatedly, we retrieve the solution if the stored key matches the summary. We incorporated the proposed mechanism into a model-checking technique with multi-swarm Particle Swarm Optimization and evaluated the search performance. We show in this paper that the proposed mechanism improved time and space consumption while maintaining solution quality.

Towards a transformation approach from SecureUML to ‎Alloy

In critical information systems, Role-Based Access Control (RBAC) has been frequently used. The specification of access control policies is an essential step in securing information systems. This article presents a transformative approach for addressing design challenges within these specifications using Model-Driven Architecture (MDA). A method is introduced for specifying and verifying model-based access control (RBAC) rules by combining SecureUML and Alloy, referred to as SecureUML2Alloy. This approach leverages transformation techniques based on metamodels to express the SecureUML source model in the Alloy target model. The SecureUML2Alloy framework allows for the generation of an initial Alloy code that can be extended with facts, functions, and predicates depending on the case. The transformative framework offers a reliable, automated mechanism for verifying security specifications in critical systems, promoting both theoretical and practical advancements in model transformation and formal verification. This method provides a pathway for future automation tools in secure system design and analysis, contributing to the reliability and security of software systems across multiple fields.

Autonomous Attack Mitigation Through Firewall Reconfiguration

ABSTRACTPacket filtering firewalls represent a main defense line against cyber attacks that target computer networks daily. However, the traditional manual approaches for their configuration are no longer applicable to next‐generation networks, which have become much more complex after the introduction of virtualization paradigms. Some automatic strategies have been investigated in the literature to change that old‐fashioned configuration approach, but they are not fully autonomous and still require several human interventions. In order to overcome these limitations, this paper proposes an autonomous approach for firewall reconfiguration where all steps are automated, from the derivation of the security requirements coming from the logs of IDSs to the deployment of the automatically computed configurations. A core component of this process is React‐VEREFOO, which models the firewall reconfiguration problem as a Maximum Satisfiability Modulo Theories problem, allowing the combination of full automation, formal verification, and optimization in a single technique. An implementation of this proposal has undergone experimental validation to show its effectiveness and performance.

Lightweight Mutually Authenticated Key Exchange with Physical Unclonable Functions

Authenticated key exchange is desired in scenarios where two participants must exchange sensitive information over an untrusted channel but do not trust each other at the outset of the exchange. As a unique hardware-based random oracle, physical unclonable functions (PUFs) can embed cryptographic hardness and binding properties needed for a secure, interactive authentication system. In this paper, we propose a lightweight protocol, termed PUF-MAKE, to achieve bilateral mutual authentication between two untrusted parties with the help of a trusted server and secure physical devices. At the end of the protocol, both parties are authenticated and possess a shared session key that they can use to encrypt sensitive information over an untrusted channel. The PUF’s underlying entropy hardness characteristics and the key-encryption-key (KEK) primitive act as the root of trust in the protocol’s construction. Other salient properties include a lightweight construction with minimal information stored on each device, a key refresh mechanism to ensure a fresh key is used for every authentication, and robustness against a wide range of attacks. We evaluate the protocol on a set of three FPGAs and a desktop server, with the computational complexity calculated as a function of primitive operations. A composable security model is proposed and analyzed considering a powerful adversary in control of all communications channels. In particular, session key confidentiality is proven through formal verification of the protocol under strong attacker (Dolev-Yao) assumptions, rendering it viable for high-security applications such as digital currency.

Advanced Security Auditing Methods for Solidity-Based Smart Contracts

The development of smart contracts remains in its early stages, with significant differences in underlying programming languages and application platforms resulting in a lack of standardization. This lack of standardization increases the susceptibility to vulnerabilities and associated financial losses. To address security vulnerabilities in smart contracts on the Ethereum blockchain platform, this paper proposes a security audit method based on formal verification. The method integrates an input module, static analysis module, formal verification module, analog execution module, and report and recommendation module, which can accurately discover the security vulnerabilities and logical flaws of smart contracts through formal verification and other analysis techniques, thus realizing correctness detection. During the experiment, the method detects 8 types of common vulnerabilities in 148 smart contracts and marks 21 smart contracts with vulnerabilities. After manual review and analysis, it is found that 17 of these 21 marked smart contracts do have security vulnerabilities. The experimental results show that the proposed method can accurately detect security vulnerabilities and logic flaws in smart contracts through formal verification and other analysis techniques before smart contracts are deployed, thus significantly improving the security of smart contracts and reducing the economic losses that may be caused by code defects.

Towards partial monitoring: Never too early to give in

Runtime Verification is a lightweight formal verification technique used to verify whether a system behaves as expected at runtime. Expected behaviour is typically formally specified using properties, which are used to automatically synthesise monitors. Properties that can be verified at runtime by a monitor are called monitorable, while those that cannot are termed non-monitorable. In this paper, we revisit the notion of monitorability and demonstrate how non-monitorable properties can still be used to generate partial monitors. We tackle this from two different perspectives: (i) by recognising that a monitor can give up on monitoring the property under analysis if it recognises that the monitoring will never conclude the satisfaction or violation of the property; (ii) by recognising that a monitor can give up on events that are not necessary for successful monitoring of the property under analysis. By considering these two aspects, we present how to achieve partial monitoring of Linear Temporal Logic properties by building upon the standard monitor construction. Finally, we present a prototype implementation of our approach and its application to a remote inspection case study, as well as a set of evaluation experiments to stress test our approach using synthetic properties.

Scaling up statistical model checking of cyber-physical systems via algorithm ensemble and parallel simulations over HPC infrastructures

Model-based formal verification of industry-relevant Cyber-Physical Systems (CPSs) is often a computationally prohibitive task. In most cases, the complexity of the models precludes any prospect of symbolic analysis, leaving numerical simulation as the only viable option. Unfortunately, exhaustive simulation of a CPS model over the entire set of plausible operational scenarios is rarely possible in practice, and alternative strategies such as Statistical Model Checking (SMC) must be used instead.In this article, we show that the number of model simulations (samples) required by SMC techniques to converge can be significantly reduced by considering multiple (an ensemble of) Adaptive Stopping Algorithms (SAs) at once, and that the simulations themselves (by far the most expensive step of the entire workload) can be efficiently sped up by exploiting massively parallel platforms.With three industry-scale CPS models, we experimentally show that the use of an ensemble of two state-of-the-art SAs (AA and EBGStop) may require dozens of millions fewer samples when compared to running a single algorithm, with reductions in sample size of up to 78%. Furthermore, we show that our implementation, by massively parallelizing system model simulations on a HPC infrastructure, yields speed-ups for the completion time of the verification tasks which are practically linear with respect to the number of computational nodes, thus achieving an efficiency of virtually 100%, even on very large platforms. This makes it possible to complete tasks of model-based SMC verification for complex CPSs in a matter of hours or days, whereas a naïve sequential execution would require from months to many years.

First order Büchi automata and their application to verification of LTL specifications

Büchi automata have applications in formal verification, e.g., in deciding whether a system satisfies given properties. We provide a definition of Büchi automata based on first order logics for representing infinite state systems, and investigate rules for proving emptiness and non-emptiness of such automata. We then apply these rules to solve the problem of verifying correctness of concurrent transition systems, leading to a relatively complete approach for proving and disproving LTL (Linear Temporal Logic) specifications. This approach overcomes weaknesses of existing work based on well-founded sets in the sense that the relative completeness does not depend on additional specification for ensuring progress of non-stuttering transitions. On the practical aspect, we provide a set of examples with an experimental verification condition generation tool to demonstrate the potential applicability of the approach for the verification of concurrent systems.