Formal Verification Algorithms Research Articles

DECLAREd: A Polytime LTLf Fragment

This paper considers a specification rewriting meachanism for a specific fragment of Linear Temporal Logic for Finite traces, DECLAREd, working through an equational logic and rewriting mechanism under customary practitioner assumptions from the Business Process Management literature. By rewriting the specification into an equivalent formula which might be easier to compute, we aim to streamline current state-of-the-art temporal artificial intelligence algorithms working on temporal logic. As this specification rewriting mechanism is ultimately also able to determine with the provided specification is a tautology (always true formula) or a formula containing a temporal contradiction, by detecting the necessity of a specific activity label to be both present and absent within a log, this implies that the proved mechanism is ultimately a SAT-solver for DECLAREd. We prove for the first time, to the best of our knowledge, that this fragment is a polytime fragment of LTLf, while all the previously-investigated fragments or extensions of such a language were in polyspace. We test these considerations over formal synthesis (Lydia), SAT-Solvers (AALTAF) and formal verification (KnoBAB) algorithms, where formal verification can be also run on top of a relational database and can be therefore expressed in terms of relational query answering. We show that all these benefit from the aforementioned assumptions, as running their tasks over a rewritten equivalent specification will improve their running times, thus motivating the pressing need of this approach for practical temporal artificial intelligence scenarios. We validate such claims by testing such algorithms over a Cybersecurity dataset.

Hierarchy Modeling and Formal Verification of Emergency Treatment Processes

Petri nets are suitable for modeling and analysis of business processes. However, the lack of data concepts often makes Petri-net-based models excessively large and difficult to analyze especially when process logic is sensitive to changes of process attribute values. Emergency treatment processes are a typical example of this situation. To solve the aforementioned problems, this paper proposes a new hierarchical Petri net model for modeling and verification of emergency treatment processes. The hierarchical Petri net model includes three separate but closely related models, i.e., a business process logic net, a business process semantic net, and a set of case models. Business process logic nets are used to model the task dependencies disregarding semantic information. Business process semantic nets introduce data concepts to business process logic nets to model semantic information such as process attributes or conditions of sequence flows. Case models are used to model the practical routes of specific business instances. Based on the three models, a formal verification algorithm of an emergency treatment process is presented. Finally, the hierarchical modeling and verification methods are validated by an emergency treatment process of highways under snow/ice weather conditions.

English

AIMS: Incorporation of autoverification algorithms in the current Laboratory Information System (LIS) for observed values of clinical chemistry examinations performed in the biochemistry department, New Civil Hospital, Surat, Gujarat. MATERIALS AND METHODS: Draw Data Flow Diagrams (DFD) based on currently used formal and informal verification algorithms used by technicians for the observed value of examinations. If required make changes in MySQL database data dictionary. Write PHP code modules to execute DFDs and incorporate code in existing LIS code. Perform software testing of LIS to find whether PHP code for autoverification yields intended results. Implement altered LIS code for patient reporting with post-implementation monitoring for errors. Compare turn around time and error done by technical staff between manual verification and Autoverification. RESULTS: Autoverification algorithm was successfully developed and implemented for various parameters. 16.75 % errors occurred during manual verification, while no error occurred during autoverification. Average TAT taken for manual verification of 20 dummy cases (reports) was approximately 32 mins verses less than 90 sec for autoverification. CONCLUSIONS: Auto-verification, if properly validated for each and every possible outcome, is error proof and fast as compared to manual verification, which results in considerable errors of commission and omission.

Formal-Analysis-Based Trace Computation for Post-Silicon Debug

This paper presents a post-silicon debug methodology that provides a means to rewind, or backspace, a chip from a known crash state using a combination of on-chip real-time data collection and off-chip formal analysis methods. A complete debug flow is presented that considers practical considerations such as area, on-chip non-determinism and signal propagation delay. This flow, along with a low-overhead breakpoint circuit, allows for state-accurate breakpointing capabilities without the need to monitor the entire state of the chip. The flow and associated hardware was tested using a hardware prototype, which consists of an OpenRISC processor instrumented with the debug hardware connected to a PC running the formal verification algorithms. Traces hundreds of cycles long were obtained using the methodology presented in this paper.

Assume–guarantee verification of nonlinear hybrid systems with Ariadne

SUMMARYIn many applicative fields, there is the need to model and design complex systems having a mixed discrete and continuous behavior that cannot be characterized faithfully using either discrete or continuous models only. Such systems consist of a discrete control part that operates in a continuous environment and are named hybrid systems because of their mixed nature. Unfortunately, most of the verification problems for hybrid systems, like reachability analysis, turn out to be undecidable. Because of this, many approximation techniques and tools to estimate the reachable set have been proposed in the literature. However, most of the tools are unable to handle nonlinear dynamics and constraints and have restrictive licenses. To overcome these limitations, we recently proposed an open‐source framework for hybrid system verification, called Ariadne, which exploits approximation techniques based on the theory of computable analysis for implementing formal verification algorithms. In this paper, we will show how the approximation capabilities of Ariadne can be used to verify complex hybrid systems, adopting an assume–guarantee reasoning approach. Copyright © 2012 John Wiley & Sons, Ltd.

Formal verification of candidate solutions for post-synthesis evolutionary optimization in evolvable hardware

We propose to utilize a formal verification algorithm to reduce the fitness evaluation time for evolutionary post-synthesis optimization in evolvable hardware. The proposed method assumes that a fully functional digital circuit is available. A post-synthesis optimization is then conducted using Cartesian Genetic Programming (CGP) which utilizes a satisfiability problem solver to decide whether a candidate solution is functionally correct or not. It is demonstrated that the method can optimize digital circuits of tens of inputs and thousands of gates. Furthermore, the number of gates was reduced for the LGSynth93 benchmark circuits by 37.8% on average with respect to results of the conventional SIS tool.

Algorithm for formal verification of business process templates

A formal definition of a business process template is presented that is based on an analysis of ITIL and MOF libraries. Definitions of an initialization precondition and an execution postcondition are introduced. The solvability of the formal verification problem for business process templates is shown under some given initialization precondition and execution postcondition. This research is planned to be continued with a view to (i) using a formal verification algorithm with other business process template libraries and (ii) examining other business process libraries to identify new classes of business processes. Translated from Kibernetika i Sistemnyi Analiz, No. 2, pp. 62---76, March---April 2011.

Parallel and Distributed Methods in Verification

The paper introduces the PDMC workhshop series and the key ideas behind the parallelization and distribution of formal verification algorithms. Further, it introduces the selection of papers from the workshop series published in the issue.

Verification method of dataflow algorithms in high-level synthesis

This paper presents a formal verification algorithm using the Petri Net theory to detect design errors for high-level synthesis of dataflow algorithms. Typically, given a dataflow algorithm and a set of architectural constraints, the high-level synthesis performs algorithmic transformation and produces the optimal scheduling. How to verify the correctness of high-level synthesis becomes a key issue before mapping the synthesis results onto a silicon. Many tools exist for RTL (Register Transfer Level) design, but few for high-level synthesis. Instead of applying Boolean algebra, this paper adopts the Petri Net theory to verify the correctness of the synthesis result, because the Petri Net model has the nature of dataflow algorithms. Herein, we propose three approaches to realize the Petri Net based formal verification algorithm and conclude the best one who outperforms the others in terms of processing speed and resource usage.

What is formal verification?

Formal verification is the use of mathematical techniques to ensure that a design conforms to some precisely expressed notion of functional correctness. Concretely, assume that you have (1) a model of a design, (2) some description of the environment that the design is supposed to operate in, and (3) some properties that the design is intended to fulfill. Given this information, you may want to search for some input patterns that the environment could generate that will violate the properties. Classical approaches to demonstrating that such input stimuli exist are random simulation, or directed test. Formal verification is an alternative approach that can be used both to search for inputs sequences that violate the properties, and prove that the properties always hold in the case when no such stimuli exist.Formal verification can be applied to designs described at many different levels of abstraction, ranging from the gate level, to RTL implementations, and in some cases even to transaction level models described in standardized programming languages.There are several different use models for formal verification. Some design teams use it to boost the coverage of random simulation and hunt for bugs, whereas others make full blown use of it to conclusively prove that certain properties hold. State-of-the-art tools integrate formal verification engines with simulation in a seamless way.A particular formal verification problem of great interest in EDA is equivalence checking. Here, the property that is checked is whether two different designs always have the same input/output behavior with respect to some notion of equivalence. Special algorithms are used when it is known that the two designs differ only in restricted ways, for example when combinational optimization only has been used to derive one from the other.Compute resources required by formal verification algorithms generally grow very quickly as design sizes increase. Current formal verification research aims to increase the capacity of the design analysis algorithms, and to make formal verification usable earlier in the design cycle. For equivalence checking, hot topics include better capacity for data path verification and support for verification of sequential transformations.