Formal Methods In Software Engineering Research Articles

Preface: Special issue on software verification and testing

Software is now everywhere and guiding every part of our daily life (Web applications, smartphones, video games, cars, information systems, etc.). Designing and developing software systems has always been a tedious and error-prone task, and the ever increasing system complexity is making matters even worse. Although we are still far from providing widespread techniques and tools avoiding the existence of bugs in a system under development, we know how to automatically chase and find bugs that would be very difficult, if not impossible, to detect manually. Software Verification and Testing is a research discipline of software engineering aiming at augmenting the quality of software by looking for bugs and checking that the developed software satisfies the expected requirements (functional and non-functional). There are several techniques for debugging and obtaining high quality software such as model checking, model-based testing, theorem proving, symbolic execution, run-time verification, fault diagnosis, or static analysis. This Special Issue (SI) is dedicated to Software Verification and Testing (SVT) and more precisely aims at contributing to the challenge of improving the usability of formal methods in software engineering. This SI is a follow-up of the SVT track that we organized at the 31th ACM Symposium on Applied Computing, held in Pisa, Italy on April 3-8, 2016. The track received 58 full paper submissions. After a careful reviewing process, the international Program Committee decided to select 13 papers for presentation during the symposium and inclusion in the SAC'16 proceedings. From these 13 papers, the five best papers were selected and invited for an extended version to this special issue. We also received new submissions since an open call circulated for this SI. All the submissions went through a rigorous peer review process; four papers were finally accepted and are included in this special issue. These papers provide key insights on different formal verification and testing approaches.

Special issue: software verification and testing

Welcome to the special issue dedicated to the selected extended papers of the Software Verification and Testing (SVT 2012) track held at the 27th ACM Symposium on Applied Computing (ACM SAC 2012). SVT 2012 attracted 43 submissions of which 12 papers were selected for presentation and publication in the proceedings of ACM SAC 2012. From these 12 papers, six were invited to the special issue and after several rigorous rounds of reviews (by at least three expert reviewers), five papers were accepted for inclusion in this special issue. This means that less than 12 percent of our initial submissions, after several rounds of review and revision, made their way into the special issue before you. The SVT track brings together academic researchers and industry R&D expertise to discuss new results in formal verification and testing, as well as development of technologies to improve the usability of formal methods in software engineering. The SVT track’s topics of interest include:

FormSERA workshop on formal methods in software engineering rigorous and agile approaches

This report summarizes the activities and results of the FormSERA workshop on Formal Methods in Software Engineering -- Rigorous and Agile Approaches. The workshop took place on the 2nd of June 2012 in Zürich (CH) under the umbrella of the 34th International Conference on Software Engineering, ICSE 2012, see http://www.formsera.org/.

Guest editorial to the special section on SEFM 2009

Software engineering is about developing large systemsusing systematic techniques. Formal methods in software engineering advocates the use of precisely defined techniques to develop software. In theory, requirements can be captured as an abstract specification and the final system obtained via suitable transformations. In practice this is not really feasible. Hence, only a small part of the actual system development process uses formal methods. Thus, there are numerous open research problems in the area of formal methods as applied to software engineering. Formal methods in software engineering can be viewed as the use of techniques that are based on mathematics (i.e., the formal aspects) in the context of practical principles applied to building software (i.e., the engineering aspects). Topics that are of interest include the use of appropriate languages/notations for the specification of systems, the refinement of specifications to code, the semantic foundations that support formal methods, the rigorous analysis of specifications and/or code that can be undertaken. The aim of this special section is to provide a collection of papers that illustrate the application of formal methods to

The Formal Design Model of an Automatic Teller Machine (ATM)

An Automated Teller Machine (ATM) is a safety-critical and real-time system that is highly complicated in design and implementation. This article presents the formal design, specification, and modeling of the ATM system using a denotational mathematics known as Real-Time Process Algebra (RTPA). The conceptual model of the ATM system is introduced as the initial requirements for the system. The architectural model of the ATM system is created using RTPA architectural modeling methodologies and refined by a set of Unified Data Models (UDMs), which share a generic mathematical model of tuples. The static behaviors of the ATM system are specified and refined by a set of Unified Process Models (UPMs) for the ATM transition processing and system supporting processes. The dynamic behaviors of the ATM system are specified and refined by process priority allocation, process deployment, and process dispatch models. Based on the formal design models of the ATM system, code can be automatically generated using the RTPA Code Generator (RTPA-CG), or be seamlessly transformed into programs by programmers. The formal models of ATM may not only serve as a formal design paradigm of real-time software systems, but also a test bench for the expressive power and modeling capability of exiting formal methods in software engineering.

The Formal Design Model of a Lift Dispatching System (LDS)

A Lift Dispatching System (LDS) is a typical real-time system that is highly complicated in design and implementation. This article presents the formal design, specification, and modeling of the LDS system using a denotational mathematics known as Real-Time Process Algebra (RTPA). The conceptual model of the LDS system is introduced as the initial requirements for the system. The architectural model of the LDS system is created using RTPA architectural modeling methodologies and refined by a set of Unified Data Models (UDMs). The static behaviors of the LDS system are specified and refined by a set of Unified Process Models (UPMs) for the lift dispatching and serving processes. The dynamic behaviors of the LDS system are specified and refined by process priority allocation and process deployment models. Based on the formal design models of the LDS system, code can be automatically generated using the RTPA Code Generator (RTPA-CG), or be seamlessly transferred into programs by programmers. The formal models of LDS may not only serve as a formal design paradigm of real-time software systems, but also a test bench of the expressive power and modeling capability of exiting formal methods in software engineering.

The Formal Design Model of a Telephone Switching System (TSS)

A typical real-time system, the Telephone Switching System (TSS), is a highly complicated system in design and implementation. This paper presents the formal design, specification, and modeling of the TSS system using a denotational mathematics known as Real-Time Process Algebra (RTPA). The conceptual model of the TSS system is introduced as the initial requirements for the system. Then, the architectural model of the TSS system is created using the RTPA architectural modeling methodologies and refined by a set of Unified Data Models (UDMs). The static behaviors of the TSS system are specified and refined by a set of Unified Process Models (UPMs) such as call processing and support processes. The dynamic behaviors of the TSS system are specified and refined by process priority allocation, process deployment, and process dispatching models. Based on the formal design models of the TSS system, code can be automatically generated using the RTPA Code Generator (RTPA-CG), or be seamlessly transformed into programs by programmers. The formal model of TSS may not only serve as a formal design paradigm of real-time software systems, but also a test bench of the expressive power and modeling capability of exiting formal methods in software engineering.

A comparative evaluation of the Z, CSP, RSL, and VDM languages

The software engineering process has been described in many ways. Today, few of these deal specifically with the use of formal methods in software engineering. New software engineering uses formal specification languages in system analysis, requirement analysis, and system design to develop software for critical-safety systems. Formal specification languages describe the system at a much higher level than a programming language. They are catego-rized into model-oriented, constructive, algebraic, process model, hybrid, and logical. This paper describes the properties and types of formal specification languages in software engineering. It then compares the Z, VDM, RSL, and CSP formal specification lan-guages from different point of views.

An Environment for the Specification And Verification of Time-Dependent Security Protocols

The use of formal methods in software engineering for the specification and the verification is suitable when developing complex systems. The distributed nature, the subtle time dependence and the strict requirements of time sensitive security protocols increase the inherent complexity of their validation. Using the TESLA authentication protocol as a case study, we shall discuss what are the functionalities that a verification environment should have to model and verify successfully a time-dependent security protocol and our environment which employs THLPSL as the modelling language and the UPPAAL model checker as the verification engine.

Formal add to traditional methods in software engineering

Traditional, informal techniques in software engineering reach their limits when complex systems are to be developed efficiently. The Institute for Formal Methods in Computer Science of the Universitat Stuttgart states: Tools like IDEs, automatic code generation from graphical descriptions, visualization techniques like UML diagrams, and others are certainly necessary. However, they often lack the ability to support detailed and provably sound reasoning about complex systems. Formal methods in software engineering provide approaches to close that gap.

Intelligent Systems and Formal Methods in Software Engineering

Over the last few years, technologies for the formal description, construction, analysis, and validation of software - based mostly on logics and formal reasoning - have matured. We can expect them to complement and partly replace traditional software engineering methods in the future. Formal methods in software engineering are an increasingly important application area for intelligent systems. The field has outgrown the area of academic case studies, and industry is showing serious interest. We convincingly argue that we've reached the point where we can solve the problem of how to formally verify industrial-scale software. We propose program verification as a computer science Grand Challenge. Deductive software verification is a core technology of formal methods. We describe recent dramatic changes in the way it's perceived and used. Another important base technique of formal methods, besides software verification, is synthesizing software that's correct by construction because it's formally derived from its specification. We discuss recent developments and trends in this area. Surprisingly efficient decision procedures for the satisfiability modulo theories problem have recently emerged. We explain these techniques and why they're important for all formal-methods tools. We look at formal methods from an industry perspective. We explain the success of Microsoft Research's SLAM project, which has developed a verification tool for device drivers

An experimental investigation of formality in UML-based development

The object constraint language (OCL) was introduced as part of the Unified Modeling Language (UML). Its main purpose is to make UML models more precise and unambiguous by providing a constraint language describing constraints that the UML diagrams alone do not convey, including class invariants, operation contracts, and statechart guard conditions. There is an ongoing debate regarding the usefulness of using OCL in UML-based development, questioning whether the additional effort and formality is worth the benefit. It is argued that natural language may be sufficient, and using OCL may not bring any tangible benefits. This debate is in fact similar to the discussion about the effectiveness of formal methods in software engineering, but in a much more specific context. This paper presents the results of two controlled experiments that investigate the impact of using OCL on three software engineering activities using UML analysis models: detection of model defects through inspections, comprehension of the system logic and functionality, and impact analysis of changes. The results show that, once past an initial learning curve, significant benefits can be obtained by using OCL in combination with UML analysis diagrams to form a precise UML analysis model. But, this result is however conditioned on providing substantial, thorough training to the experiment participants.

A graphical user interface for editing formal specification objects

Extensive tool support is critical for increasing the usefulness and industrial acceptance of formal software engineering methods. In previous work, we have developed a technique for executing form...

The Real-Time Process Algebra (RTPA)

The real-time process algebra (RTPA) is a set of new mathematical notations for formally describing system architectures, and static and dynamic behaviors. It is recognized that the specification of software behaviors is a three-dimensional problem known as: (i) mathematical operations, (ii) event/process timing, and (iii) memory manipulations. Conventional formal methods in software engineering were designed to describe the 1-D (type (i)) or 2-D (types (i) and (iii)) static behaviors of software systems via logic, set and type theories. However, they are inadequate to address the 3-D problems in real-time systems. A new notation system that is capable to describe and specify the 3-D real-time behaviors, the i>real-time process algebra (RTPA), is developed in this paper to meet the fundamental requirements in software engineering. RTPA is designed as a coherent software engineering notation system and a formal engineering method for addressing the 3-D problems in software system specification, refinement, and implementation, particularly for real-time and embedded systems. In this paper, the RTPA meta-processes, algebraic relations, system architectural notations, and a set of fundamental primary and abstract data types are described. On the basis of the RTPA notations, a system specification method and a refinement scheme of RTPA are developed. Then, a case study on a telephone switching system is provided, which demonstrates the expressive power of RTPA on formal specification of both software system architectures and behaviors. RTPA elicits and models 32 algebraic notations, which are the common core of existing formal methods and modern programming languages. The extremely small set of formal notations has been proven sufficient for modeling and specifying real-time systems, their architecture, and static/dynamic behaviors in real-world software engineering environment.

Debugging VHDL designs using model-based reasoning

The application of formal methods in software engineering and hardware design has become an important field of research. It aims at minimizing time to market and reduce the overall development costs. While formal verification, e.g. model-checking, is widely used, methods for helping programmers or engineers in locating and fixing faults within a hardware design or software are rarely available. In this paper we describe part of the advanced diagnosis and measurement selection capabilities of the model-based diagnosis tool VHDLDIAG designed for (semi)automatically locating bugs in VHDL programs. VHDL is an Ada-like and widely used hardware description language. VHDL programs are converted into logical descriptions which are then used by a diagnosis engine for detecting the parts of the program responsible for an observed misbehavior. The results of diagnosis, i.e. the malfunctioning program fragments, are mapped back to the program code. Because of the logical description used VHDLDIAG can be applied to a wide range of programs from small to very large ones with up to thousands of MBytes of source code. This paper presents techniques which use multiple versions of a design in diagnosis, as well as the measurement selection process used in VHDLDIAG. Formal definitions and performance results using real-world VHDL programs are given.

Using formal methods for teaching software engineering: a tool-based approach

In this paper we describe and review the course plan and syllabus we use in a course on formal methods in software engineering currently included in the degree in Informatics of the Faculty of Sciences at the University of Bologna. The course matches the theory of formal methods with their practice based on actual tool usage. In fact, the course is centered upon a project whose main goal is to let students learn some formal specification techniques, all supported by specific tools. The students use welldknown notations for both requirements specification and formal design. The formal methods we use are based on the Z notation for requirements specification and on the Larch family of languages for design specifications.

Software development with Z. A practical approach to formal methods in software engineering

1. Introduction 2. A Simple Z Specification 3. Sets and Predicates 4. Relations and Functions 5. Schemas and Specifications 6. Data Design 7. Algorithm Design

Introduction to Formal Methods for Software Engineering

This paper describes what is meant by formal methods for software engineering. It is intended for the non-mathematical reader, and a simple formal specification is presented. The process of formal specification, development and proof is described briefly. Finally the benefits and limitations of formal methods are summarized.

Education in formal methods for software engineering

Education and consultancy are key to the introduction of software engineering methods into the development process. Software engineering is a new activity, not just a way of writing better programs. It is demanding in its recording and communication requirements. Mathematics plays an important part. Software engineering education must teach many new skills. A workshop teaching these skills has been running over three years.

Formal specification and rapid prototyping: building in quality at the start

Formal Methods for Software Engineering, although widely recognised in academe as of potential benefit to industry, have proved difficult to sell, both to industry and to students. Building on a novel teaching approach at Coventry University, we present an integrated approach to formal specification and rapid prototyping that offers a real contribution to building in quality at the front end of the development lifecycle. The significance of formal specification and rapid prototyping for software development are discussed. An introduction is given to the functional programming language Miranda™, the vehicle for our approach. An extended type structure is presented for Miranda, providing an executable specification language based on simple settheoretical structures. We are thus enabled to construct directly executable specifications which serve as rapid prototypes, useful for early requirements analysis and refinement. An explanatory example is presented to show the utility of the approach in building quality systems. Z text is included to show the applicability of the approach to formal specifications expressed in languages such as Z and VDM. The example is further used to describe our HCI-builder tool, which enables the user to quickly produce a functional user interface to her prototype application.