For Field Programmable Gate Array Device Research Articles

Development of Multiobjective High-Level Synthesis for FPGAs

Traditionally, the High-Level Synthesis (HLS) for Field Programmable Gate Array (FPGA) devices is a methodology that transforms a behavioral description, as the timing-independent specification, to an abstraction level that is synthesizable, like the Register Transfer Level. This process can be performed under a framework that is known as Design Space Exploration (DSE), which helps to determine the best design by addressing scheduling, allocation, and binding problems, all three of which are NP-hard problems. In this manner, and due to the increased complexity of modern digital circuit designs and concerns regarding the capacity of the FPGAs, designers are proposing novel HLS techniques capable of performing automatic optimization. HLS has several conflicting metrics or objective functions, such as delay, area, power, wire length, digital noise, reliability, and security. For this reason, it is suitable to apply Multiobjective Optimization Algorithms (MOAs), which can handle the different trade-offs among the objective functions. During the last two decades, several MOAs have been applied to solve this problem. This paper introduces a comprehensive analysis of different MOAs that are suitable to perform HLS for FPGA devices. We highlight significant aspects of MOAs, namely, optimization methods, intermediate structures where the optimizations are performed, HLS techniques that are addressed, and benchmarks and performance assessments employed for experimentation. In addition, we show the analysis of how multiple objectives are optimized currently in the algorithms and which are the objective functions that are optimized. Finally, we provide insights and suggestions to contribute to the solution of major research challenges in this area.

A high-performance, resource-efficient, reconfigurable parallel-pipelined FFT processor for FPGA platforms

The fast Fourier transform (FFT) algorithm is widely used in digital signal processing systems (DSPs); hence, the development of a high-performance and resource-efficient FFT processor that conforms to the processing and precision requirements of real-time signal processing is highly desirable. We propose an FFT processor for field programmable gate array (FPGA) devices, based on the radix-2-decimation-in-frequency (R2DIF) algorithm. An appropriately modified parallel double-path delay commutator (DDC) architecture for radix-2 with continuous dual-input and dual-output streams (CoDIDOS) is proposed to increase throughput and reduce latency in FFT computation. The chip-area of the proposed design is reduced by decreasing the memory footprint of the complex twiddle factor multipliers. A multiplication scheme based on a combination of the unrolled coordinate rotation digital computer (CORDIC) and the canonical signed digit-based binary expression (CSDBE) is used to multiply the complex twiddle factors without requiring memory blocks for their storage. The CSDBE technique is proposed to optimize the multiplication of constants in the architecture. The proposed FFT processor is implemented as an intellectual property (IP) core and tested on a Xilinx Virtex-7 FPGA. Experimental results confirm that the proposed design improves the speed, latency, throughput, accuracy, and resource utilization of computation on FPGA devices over existing designs.

A counting-weighted calibration method for a field-programmable-gate-array-based time-to-digital converter

In this work, we propose a counting-weighted calibration method for field-programmable-gate-array (FPGA)-based time-to-digital converter (TDC) to provide non-linearity calibration for use in positron emission tomography (PET) scanners. To deal with the non-linearity in FPGA, we developed a counting-weighted delay line (CWD) to count the delay time of the delay cells in the TDC in order to reduce the differential non-linearity (DNL) values based on code density counts. The performance of the proposed CWD-TDC with regard to linearity far exceeds that of TDC with a traditional tapped delay line (TDL) architecture, without the need for nonlinearity calibration. When implemented in a Xilinx Vertix-5 FPGA device, the proposed CWD-TDC achieved time resolution of 60ps with integral non-linearity (INL) and DNL of [−0.54, 0.24] and [−0.66, 0.65] least-significant-bit (LSB), respectively. This is a clear indication of the suitability of the proposed FPGA-based CWD-TDC for use in PET scanners.

Low Latency Network-on-Chip Router Microarchitecture Using Request Masking Technique

Network-on-Chip (NoC) is fast emerging as an on-chip communication alternative for many-core System-on-Chips (SoCs). However, designing a high performance low latency NoC with low area overhead has remained a challenge. In this paper, we present a two-clock-cycle latency NoC microarchitecture. An efficient request masking technique is proposed to combine virtual channel (VC) allocation with switch allocation nonspeculatively. Our proposed NoC architecture is optimized in terms of area overhead, operating frequency, and quality-of-service (QoS). We evaluate our NoC against CONNECT, an open source low latency NoC design targeted for field-programmable gate array (FPGA). The experimental results on several FPGA devices show that our NoC router outperforms CONNECT with 50% reduction of logic cells (LCs) utilization, while it works with 100% and 35%~20% higher operating frequency compared to the one- and two-clock-cycle latency CONNECT NoC routers, respectively. Moreover, the proposed NoC router achieves 2.3 times better performance compared to CONNECT.

Activity-Based Resource Allocation for Motion Estimation Engines

An architecture proof-of-concept which adapts the throughput datapath based on the anticipation of computational demand in dynamic environments is demonstrated and evaluated for a motion estimation (ME) engine. The input signal characteristics are exploited to anticipate the time varying computational complexity as well as to instantiate dynamic replicas (DRs) to realize fault-resilience. The scheme employs amorphous processing elements (APEs) which either perform as active elements (AEs) to maintain quality/throughput, serve as DRs to increase reliability levels, or hibernate passively as reconfigurable slack (RS) available to other tasks. Experimental results from a hardware platform for field programmable gate array (FPGA)-based video encoding demonstrate power efficiency and fault-tolerance of the ME engine. A significant reduction in power consumption is achieved ranging from 83% for low-motion-activity scene's to 12.5% for high motion activity video scenes. The scenes motion activity is utilized to improve redundancy for the purpose of priority based diagnosis of the computing modules. In addition, a graceful degradation strategy is developed to recover from hard errors by adapting the search range of candidate motion vectors (MVs). This adaptive hardware scheme is shown to automatically demote the faulty resources in FPGA devices based on streaming performance.

Secure Dual-Core Cryptoprocessor for Pairings Over Barreto-Naehrig Curves on FPGA Platform

This paper is devoted to the design and the physical security of a parallel dual-core flexible cryptoprocessor for computing pairings over Barreto-Naehrig (BN) curves. The proposed design is specifically optimized for field-programmable gate-array (FPGA) platforms. The design explores the in-built features of an FPGA device for achieving an efficient cryptoprocessor for computing 128-bit secure pairings. The work further pinpoints the vulnerability of those pairing computations against side-channel attacks and demonstrates experimentally that power consumptions of such devices can be used to attack these ciphers. Finally, we suggest a suitable countermeasure to overcome the respective weaknesses. The proposed secure cryptoprocessor needs 1 730 000, 1 206 000, and 821 000 cycles for the computation of Tate, ate, and optimal-ate pairings, respectively. The implementation results on a Virtex-6 FPGA device shows that it consumes 23 k Slices and computes the respective pairings in 11.93, 8.32, and 5.66 ms.

A Novel Method for Computing Exponential Function Using CORDIC Algorithm

In this paper, design of Coordinate Rotation Digital Computer (CORDIC) based 2D Gaussian function and an efficient Very Large Scale Integration (VLSI) architecture suitable for Field Programmable Gate Array (FPGA) implementation is presented. The potential application of the proposed 2D Gaussian function includes image enhancement, smoothing, edge detection, filtering etc. The proposed algorithm uses expanded range of CORDIC algorithm since the conventional technique converges within the range of [-1.12, +1.12]. The architectures developed exploits high degrees of pipelining and parallel processing in order to achieve real time performance. The design has been realized using Register Transfer Language (RTL) compliant Verilog code and fits into a single chip with a gate count utilization of 75,151. The algorithm has been tested for Gaussian based image smoothening application and is implemented on XC2V1000-6bg575 Xilinx FPGA device. The architecture developed is capable of processing one pixel per clock cycle and provides results in real time. The experimental results shows that the proposed approach exhibits better performance when compared with the other researcher methods.

Evaluation of Random Delay Insertion against DPA on FPGAs

Side-channel attacks (SCA) threaten electronic cryptographic devices and can be carried out by monitoring the physical characteristics of security circuits. Differential Power Analysis (DPA) is one the most widely studied side-channel attacks. Numerous countermeasure techniques, such as Random Delay Insertion (RDI), have been proposed to reduce the risk of DPA attacks against cryptographic devices. The RDI technique was first proposed for microprocessors but it was shown to be unsuccessful when implemented on smartcards as it was vulnerable to a variant of the DPA attack known as the Sliding-Window DPA attack. Previous research by the authors investigated the use of the RDI countermeasure for Field Programmable Gate Array (FPGA) based cryptographic devices. A split-RDI technique was proposed to improve the security of the RDI countermeasure. A set of critical parameters was also proposed that could be utilized in the design stage to optimize a security algorithm design with RDI in terms of area, speed and power. The authors also showed that RDI is an efficient countermeasure technique on FPGA in comparison to other countermeasures. In this article, a new RDI logic design is proposed that can be used to cost-efficiently implement RDI on FPGA devices. Sliding-Window DPA and realignment attacks, which were shown to be effective against RDI implemented on smartcard devices, are performed on the improved RDI FPGA implementation. We demonstrate that these attacks are unsuccessful and we also propose a realignment technique that can be used to demonstrate the weakness of RDI implementations.

Coefficient-dependent logic synthesis of FIR digital filters

This paper suggest aa new coefficient-dependent multiplication scheme for Field-Programmable Gate-Array (FPGA) implementation of direct-from Finite Impulse Response (FIR) digital filters. Using conventional design methods, FPGA devices are not very efficient in digital FIR filter implementation due to the plexity of the multipliers. Analysis of filter coefficients shows that a large number of redundant leading sign bits can be found in their two's-complement binary representation. Coefficient-dependent multiplier logic synthesis decreases the number of Configurable Logic Blocks (CLBs) needed by 30–40%, determined by the filter order and the selected coefficient accuracy. Memory-based bit-serial distributed multiplier and accumulator units (DMACs) can be used effectively to realize multipliers of different coefficient size on the XILINX XC4000 third-generation FPGA family.