Folded Cascode Op-amp Research Articles

Modeling and Design of A Compact Low Power Folded Cascode OpAmp With High EMI Immunity

Modeling and Design of A Compact Low Power Folded Cascode OpAmp With High EMI Immunity

Design of folded cascode op amp and its application – bandgap reference circuit

PurposeReference voltage or current generators are an important requirement for an analog or digital circuit design. Bandgap reference circuits (BGR) are most common way of generating the reference voltage. This paper aims to provide a detailed insight of design of a folded cascode operational amplifier (FC op amp) and a BGR circuit. The complete study flow from design to layout of the circuits on 180 nm semiconductor laboratory (SCL) process leading to bonding diagram for possible tape-out is discussed. This study work has been supported by MeitY, Govt. of India, through Special Manpower Development Project Chip to System Design.Design/methodology/approachThis paper provides a detailed insight in design of a FC op amp and a BGR circuit. The complete study flow from design to layout of the two circuits on 180 nm SCL process leading to bonding diagram for possible tape-out is discussed. Section 2 shows the design of FC op amp, beta-multiplier circuit and their simulation results. Section 3 describes the comparison of design of conventional BGR and the proposed BGR with other state-of-art BGR circuits. Section 4 gives the comparison of their performance. The conclusion is given in Section 5.FindingsThe post-layout simulation of FC op amp show an open-loop gain of 64.5 dB, 3-dB frequency of 5.5 KHz, unity-gain bandwidth of 8.7 MHz, slew rate of 8.4 V/µs, CMRR of 111 dB and power of 25.5µW. Among the two BGR designs, the conventional BGR generated 693 mV of reference voltage with a temperature coefficient of 16 ppm/°C the other BGR, with curvature correction generated 1.3 V of reference voltage with a temperate coefficient of 6.3 ppm/°C , both results in temperature ranging from −40°C to 125°C. The chip layout of the circuits designed on 180 nm SCL process ensures design rule check (DRC), Antenna and layout versus schematic (LVS) clean with metal fill.Research limitations/implicationsSlew rate, stability analysis, power are important parameters which should be taken care while designing an op amp for a BGR. Direct current gain should be kept higher to reduce offset errors. Input common mode range is decided by the operating temperature range. A higher power supply rejection ratio will reduce BGR sensitivity to supply voltage variations. Input offset should be kept low to reduce BGR error in reference voltage. However, this paper emphasis on the flow from schematic to layout using simulation tools. As part of the study, the bonding diagram for tape-out of BGR and FC design in the given SCL frame size with seal ring is also explored, for possible tape-out.Practical implicationsReference voltage or current generators are an important requirement for an analog or digital circuit design. BGR are most common way of generating the reference voltage. This paper provides a detailed insight in design of a FC op amp and a BGR circuit. The complete study flow from design to layout of the circuits on 180 nm SCL process leading to bonding diagram for possible tape-out is discussed. The chip layout of the circuits was designed on 180 nm SCL process ensuring DRC, antenna and LVS clean with metal fill using Cadence virtuoso and Mentor Graphics Calibre simulation tools.Social implicationsBGR are most common way of generating the reference voltage. This paper gives a detailed insight of a BGR design using a folded-cascode operational amplifier. The FC op amp is biased using a beta multiplier circuit and high-swing cascode current mirror circuit. The paper discuss FC circuit design flow from schematic to layout.Originality/valueFC op amp is biased using a beta multiplier circuit and high-swing cascode current mirror. The paper discusses FC design flow from schematic to layout. The circuits were designed on 180 nm SCL technology with 1.8 V of power supply. The post-layout simulation show an open-loop gain of 64.5 dB, 3 dB frequency of 5.5 KHz, unity-gain bandwidth of 8.7 MHz, slew rate of 8.4 V/µs, CMRR of 111 dB and power of 25.5 µW. BGR were designed using FC op amp. The proposed BGR generated 1.3 V of reference voltage with a temperature coefficient of 6.3 ppm/°C in the range from −40°C to 125°C in schematic simulation.

Gain Boosted Folded Cascode Op-Amp with Capacitor Coupled Auxiliary Amplifiers

A novel gain boosted folded cascode Op-Amp using simple single stage auxiliary amplifiers is presented. The proposed auxiliary amplifiers are designed in a way that have proper input and output DC common mode voltage without using common mode feedback network. The inputs of the auxiliary amplifiers are insulated by the coupling capacitors and floating-gate MOS transistors. Thus, the DC input voltage level limit has been removed. Diode connected transistors are also used in the output of the auxiliary amplifiers, which keep the output voltage level at the desired. A simple single stage auxiliary amplifier imposes fewer poles and zeroes on the main amplifier compared to more complicated amplifiers where consumes also less power consumption. Simulation results in a 0.18μm CMOS technology show a DC gain enhancement of about 20dB while output swing, slew rate, settling time, phase margin and gain-bandwidth retain almost as the same as previous folded cascode design.

COPRICSI: COnstraint-PRogrammed Initial Circuit SIzing

This paper presents a new method to automate the sizing of analog circuits. The method emulates the manual design procedure. The sizing task is formulated as a constraint programming problem. Two new algorithms are introduced: First, a hierarchical structural analysis of functional blocks that automatically sets up the analytical equations for the sizing. And second, a heuristic to guide the branching process of a constraint programming solver. We achieve a reproduction of the manual proceeding of designers and at the same time an automation of the set-up of the design problem, reducing the set-up effort to seconds. The method is primarily designed for operational amplifiers. More than 20 circuits, including different variants of two-stage, folded-cascode, telescopic and symmetrical op-amps, are considered at this time. This paper presents a runtime comparison of the newly developed branching heuristic with a generic branching heuristic on 20 different circuits. Furthermore, sizing results for a two-stage op-amp with transistors in weak inversion and a folded-cascode op-amp with common-mode feedback circuit are presented to show the effectiveness of the approach.

Design of PMOS and NMOS Input Folded Cascode Amplifier using 180nm SCL Technology Node for Low Power Application

This paper presents the details design and simulation of the Folded Cascode amplifier using Source-Coupled-Logic (SCL) technology node for both the P-Type Metal Oxide Semiconductor (PMOS) and N-Type Metal Oxide Semiconductor (NMOS) input. The different way to implement the circuit design for a given specification has clearly described including all the design equation has been presented. All the parameter like open loop gain, Unity Gain Bandwidth (UGB) and Phase Margin (PM) are compared for both the NMOS and PMOS input fully differential folded cascode op-amp circuit are discussed and finally we have got after performance analysis that NMOS input fully differential folded cascode op-amp is the best choice for low power high speed application like in pipeline Analog to Digital (ADC). The circuit has been simulated using cadence virtuoso tool in 0.18μm SCL technology node.

Design and Comparative Analysis of Folded Cascode OP-AMP with Different Input Stages

The work done represents the overall structure and comparative analysis of folded cascode operational amplifier (op-amp) in fully differential configuration having PMOS and NMOS input stages with robust biasing and common mode feedback circuit under different process, voltage and temperature variations in 180nm technology with 1.8V power supply and 1pf load resulting in good optimization among the parameters such as gain, bandwidth, phase margin and power dissipation.

A Start-up Assisted Fully Differential Folded Cascode Opamp

This paper explains the hidden positive feedback in a two-stage fully differential amplifier through external feedback resistors and possible DC latch-up during the amplifier start-up. The biasing current selection among the cascade branches has been explained intuitively, with reference to previous literature. To avoid the latch-up problem, irrespective of the transistor bias currents, a novel hysteresis-based start-up circuit is proposed. An 87[Formula: see text]dB, 250[Formula: see text]MHz unity gain bandwidth amplifier has been developed in 65[Formula: see text]nm CMOS Technology and post-layout simulations demonstrate no start-up failures out of 1000 Monte-Carlo (6-Sigma) simulations. The circuit draws 126[Formula: see text][Formula: see text]A from a 1.2[Formula: see text]V supply and occupies the 2184[Formula: see text][Formula: see text]m2 area.

An enhanced fast slew rate recycling folded cascode Op-Amp with general improvement in 180 nm CMOS process

This paper presents a new technique to improve CMOS recycling folded cascode (RFC) operational amplifier (Op-Amp). Our modification is based on shorting two nodes in the conventional RFC circuit. It causes that the seen resistance from the created new node be half of the conventional RFC counterpart and makes it to double the slew rate. Compared to it, our circuit is also capable to enhance DC gain and unity gain bandwidth (UGBW) with increasing output resistance of differential pair. Moreover, our proposed improvements are in better fast-settling time, input referred noise, input offset voltage, total harmonic distortion (THD), common mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) in the same power consumption. Simulation results in 180 nm CMOS process indicates that the proposed amplifier has 1.5 times the unity gain bandwidth (185 MHz versus 125 MHz) and also has 7 times gain boosting (75 dB versus 58 dB) with better figure of merit (FOM) in the same power consumption, driving capacitor load of 10 pF @1.2 V power supply. The results also demonstrate that the temperature sensitivity, power supply variations and process corners have a negligible effect on the proposed amplifier stability.

An enhanced fast-settling recycling folded cascode Op-Amp with improved DC gain in 90 nm CMOS process

Proposed in this paper is design and analysis of an enhanced recycling folded cascode (RFC) Op-Amp. This structure is achieved using connecting two nodes and eliminating some devices in the conventional RFC. This effect enhances the DC gain with increasing output resistance of differential pair compared to the conventional RFC circuit. In the same − 3 dB frequency, the unity gain bandwidth is also increased. Moreover, for the same slew rate and input referred noise performance, other proposed improvements are the fast-settling time and total harmonic distortion. Hspice simulation results in 90 nm CMOS standard technology demonstrate that the proposed amplifier has 1.2 times the unity gain bandwidth (190 vs. 160 MHz) and also has twice gain boosting (66.2 vs. 59.5 dB) in the same − 3 dB frequency, power supply (1.2 V) and driving capacitor load of 5 pF.

An efficient method of Pareto-optimal front generation for analog circuits

In this paper, an efficient deterministic methodology for generating Pareto-optimal front (PoF) of analog circuits is proposed. The proposed methodology utilizes modified epsilon constraint method along with geometric programming based circuit sizer to determine the Pareto-optimal points (PoPs) of the analog circuits. The generated PoPs are then modeled to generate the PoFs. The efficiency of the proposed methodology and the accuracy of the generated PoF has been verified with respect to that of the commonly used stochastic approach. It is found that to generate PoF having similar spread, the proposed methodology takes only 20 min whereas the stochastic approach takes 60 h. It also has been observed that the accuracy of the generated PoF using the proposed methodology improved by more than 10% with respect to that of the stochastic approach. The proposed methodology has been implemented to generate the PoF of a two-stage Op-Amp, fully differential folded cascode Op-Amp, fully differential single-stage and two-stage Op-Amps. The generated PoFs have been utilized for (1) feasibility checking for a user given specification of an Op-Amp, (2) performance prediction and (3) topology selection of the analog circuit. As per authors’ knowledge, this is the first paper which deals with all the aspects, i.e., generation, modeling and application of the PoF of the analog circuits.

DESIGN AND SIMULATION OF CURRENT FEEDBACK OPERATIONAL AMPLIFIER IN 180nm AND 90nm CMOS PROCESSES

This paper proposes a Current Feedback Operational Trans???conductance Amplifier (CFB OTA) with a folded cascode op-amp as input stage cascaded with class AB buffer as output stage. This gives better results on parameters such as bandwidth, slew rate, settling time and input offset voltage compared to the conventional CFOA. Hence it carries significance in high frequency applications such as A/D converters and active filters where CMOS CFOA used as an active building block. CADENCE simulation results are obtained using 180nm CMOS process (supply voltage of ±2.5V, 100μA biasing current) and 90nm CMOS process (supply voltage of ±1.2V, 50μA biasing current). Some of the performance parameters obtained are DC gain of 60.2dB, open-loop gain bandwidth product(GBW) of 307 MHz, slew rate (SR+) of +30V/μS to +90V/μS and DC input offset voltage of −0.6nV.

A new hybrid algorithm for analog ICs optimization based on the shrinking circles technique

This paper presents a novel technique named the Shrinking Circles to enhance the performance of optimization algorithms embedded in automated sizing tools of analog ICs. This technique creates a balance between the exploration and exploitation capabilities when the optimization algorithm is converging to a possible optimum point. With the help of the shrinking circles concept, we upgrade a hybridization version of Gravitational Search Algorithm with Particle Swarm Optimization (Advanced GSA_PSO). Accordingly, a developed tool for the automation of analog ICs sizing is proposed. The performance of this tool is evaluated by two cases: minimizing the power consumption of a two-stage CMOS op-amp and simultaneous minimizing the circuit area and power consumption of a folded-cascode op-amp. In this paper, the corners analysis is also incorporated into the proposed circuit sizing tool based on a straightforward procedure by which this tool not only can obtain the solutions being robust against process, voltage, and temperature (PVT) variations, but also it alleviates the computational burden. Comparisons with available methods show that the proposed tool performs much better in terms of efficiency.

Dc-gain enhanced folded cascode Op-amp using a new positive feedback method

In this paper, a novel operational amplifier is demonstrated which is established on the folded cascode Op-amp structure. A new technique of positive feedback is proposed to increase the open loop gain of Op-amp while not limiting its linearity. The proposed structure is simulated by HSPICE software using level 49 parameters (BSIM3V3) in a typical 0.18 µm CMOS technology. HSPICE simulation verifies the theoretical estimated improvements.

A new gain-enhanced and slew-rate-enhanced folded-cascode op amp

This paper describes a gain enhancement method and also a slew-rate enhancement scheme for folded-cascode amplifiers which uses positive feedback + transconductance increaser method for the sake of...

Low Power Personalized ECG Based System Design Methodology for Remote Cardiac Health Monitoring

This paper describes a mixed-signal electrocardiogram (ECG) system for personalized and remote cardiac health monitoring. The novelty of this paper is fourfold. First, a low power analog front end with an efficient automatic gain control mechanism, maintaining the input of the ADC to a level rendering optimum SNR and the enhanced recyclic folded cascode opamp used as an integrator for $\Sigma \Delta $ ADC. Second, a novel on-the-fly PQRST boundary detection (BD) methodology is formulated for finding the boundaries in continuous ECG signal. Third, a novel low-complexity ECG feature extraction architecture is designed by reusing the same module present in the proposed BD methodology. Fourth, the system is having the capability to reconfigure the proposed low power ADC for low (8 b) and high (12 b) resolution with the use of the feedback signal obtained from the digital block when it is in processing. The proposed system has been tested and validated on patient’s data from PTBDB, CSEDB, and in-house IIT Hyderabad Data Base (IITHDB) and we have achieved an accuracy of 99% upon testing on various normal and abnormal ECG signals. The whole system is implemented in 180-nm technology resulting in 9.47- $\mu \text{W}$ (at 1 MHz) power consumption and occupying 1.74- $mm^{2}$ silicon area.

An efficient design of CMOS comparator and folded cascode op-amp circuits using particle swarm optimization with an aging leader and challengers algorithm

Due to the compl ex growth in very large scale integration circuits, the task of optimal analog integrated circuit design by hand is very difficult. Optimization is a time consuming process having many conflicting criteria and a wide range of design parameters. Characterization of complex tradeoffs between nonlinear objectives while assuring required specifications makes analog circuit design a tedious process. The design and optimization processes have to be automated with high accuracy. Evolutionary technique may be a proficient implement for automatic design of analog integrated circuits that has been one of the most challenging topics in VLSI design process. This paper presents a competent approach for optimal designs of two analog circuits, namely, complementary metal oxide semiconductor two-stage comparator with P-type metal oxide semiconductor input driver and n-channel input, folded-cascode operational amplifier. The evolutionary technique used is particle swarm optimization (PSO) with an aging leader and challenger (ALC-PSO). The main aim is to optimize the MOS transistors’ sizes using ALC-PSO in order to reduce the areas occupied by the circuits and to get better performance parameters of the circuits. To exhibit the performance parameters of the circuits, simulation program with integrated circuit emphasis simulation has been carried out by using the optimal values of MOS transistor sizes and other design parameters. Simulation results demonstrate that design specifications are closely met and required functionalities are accommodated. The simulation results also show that the ALC-PSO is superior to the other algorithms in terms of MOS area, and performance parameters like gain, power dissipation, etc. for the examples considered.

Design of a folded cascode opamp with increased immunity to conducted electromagnetic interference in 0.18 μm CMOS

This paper presents a folded cascode CMOS instrumentation amplifier input stage with an increased immunity to electromagnetic interference (EMI): this structure is based on a recycling folded cascode topology, and has been designed in a 0.18μm UMC CMOS process. Measurements illustrate that the modified recycling folded cascode exhibits an increased EMI immunity while preserving a satisfactory frequency response.

A FAST AND LOW SETTLING ERROR CONTINUOUS-TIME COMMON-MODE FEEDBACK CIRCUIT BASED ON DIFFERENTIAL DIFFERENCE AMPLIFIER

A high-speed and high-accuracy continuous-time common-mode feedback block (CMFB) is presented. To satisfy speed and accuracy requirements, some modifications have been applied on differential difference amplifier (DDA) CMFB circuit. The proposed method is applied to a folded cascode op-amp with power supply of 3.3 V. In order to verify the proposed circuit, simulations are done in 0.35 μm standard CMOS technology. In the worst condition when the output common-mode (CM) voltage is initialized to VCC or GND, only 1.1 ns is required to set the output CM voltage on the desired level. Also in a wide range of input CM voltage variations, the deviation of the output CM voltage from reference voltage is less than 6 mV, so simulation results confirm the expected accuracy and speed while simultaneously the proposed CMFB circuit preserves other characteristics of DDA CMFB circuit such as unity gain frequency, 3-dB bandwidth, phase margin and linearity.

Design of 0. 13um CMOS Low Voltage Rail to Rail Fully Differential Operational Amplifier Review

An operational amplifier is one of the most commonly used components in analog and digital circuit designs. Low voltage and low power operational amplifier design has become an increasingly interesting subject as many applications switch to portable battery powered operations. The need for design techniques to allow amplifiers to maintain an acceptable level of performance when the supply voltages are decreased is immense. One of the most important features in low voltage amplifier designs is ensuring that the amplifier maintains constant behavior in the presence of rail-to-rail input common mode variations while providing a rail-to-rail output to maximize signal-to-noise ratio. As the supply voltage to a standard CMOS op-amp is reduced, the input common mode range and the output swing get reduced drastically. Special circuits have to be used to raise them up to rail-to-rail supply voltage. In this work we propose a design of a low-voltage CMOS rail-to-rail folded cascode operational amplifier to be realized in a standard 130 nm CMOS technology with 1.2V supply voltage and consumes power less than 400uW. A two stage miller compensated folded cascode op-amp has a UGB >10MHz and achieves a gain >80dB over almost full range of the common mode input voltage.

A Novel Low Noise High Gain CMOS Instrumentation Amplifier for Biomedical Applications

This work describes a novel technique of designing a low noise high gain CMOS instrumentation amplifier for biomedical applications. A three op-amp instrumentation amplifier have been designed by employing two simple op-amps at the two inputs and a folded cascode op-amp at the output. Both input and output stage op-amps are 2-stage. Most of the earlier designed op-amp in literature uses same type of op-amp at the input and output stages of instrumentation amplifier. By using folded cascode two stage op-amp at the output, we have achieved significant improvement in gain and CMRR. Transistors sizing plays a vital role in achieving high gain and CMRR. To achieve a desirable gain, common mode rejection ratio and other performance metrics, selection of most appropriate op-amp circuit topologies & optimum transistor sizing was the main criteria for design of instrumentation amplifier for biomedical applications. The instrumentation amplifier is simulated using Cadence Spectre tool and layout is designed in Cadence Layout editor at 0.18µm CMOS technology. Each of the input op-amp provides a gain and CMRR of 45dB and 72dB respectively. The output stage folded cascode amplifier provides a gain of 82dB and a CMRR of 92dB. The design achieves an overall gain and CMRR of 67dB and 92db respectively. The designed instrumentation amplifier consumes only 263µW of power suitable for biomedical signal processing applications. DOI: http://dx.doi.org/10.11591/ijece.v3i4.3170