Floating-point Multiplication Research Articles

Hybrid Radix-16 booth encoding and rounding-based approximate Karatsuba multiplier for fast Fourier transform computation in biomedical signal processing application

Multiplication is an essential biomedical signal processing function implemented in the Digital Signal Processing (DSP) cores. To enhance the speed, area and energy efficiency of DSP cores, approximate multiplication is used. Also, low power multiplier unit design is one of the requirements of DSP processor to meet the increasing demands. To balance both the design and error metrics of a multiplier design, an efficient Hybrid Radix-16 Booth Encoding and rounding-based approximate Karatsuba Multiplier (RBEKM-16) is proposed. This research introduces an Approximate Karatsuba multiplier based on rounding, utilizing rounding approximation to compute the least significant part of the product. Simple operators, like adders and multiplexers, replace complex and costly conventional Floating-Point (FP) multipliers in this process. Radix-4 logarithms are incorporated to further minimize hardware complexity and calculate the product's most significant part. Subsequently, an approximate 4-2 compressor is applied in the partial product reduction stage to generate the most significant bit result. In the experimental scenario, the efficiency of the multiplier is evaluated in terms of energy efficiency, area utilization and error rate by using Xilinx ISE 8.1i tool. The results from the experiments indicate that the suggested multiplier demonstrates improved energy efficiency, utilizes space more effectively, and performs well in applications related to biomedical signal processing. Further, the accomplished area utilization of the proposed 16-bit multiplier is 1068 μm2, delay is 3.01 ns, power consumption is 0.021 mW and power delay product is 119 fJ.

Design of floating point multiplier using approximate hybrid Radix-4/ Radix-8 booth encoder for image analysis

This paper presents a novel power efficient Hybrid floating point multiplier (HFPM) with approximate hybrid radix-4/radix-8 booth encoder. This approach efficiently increases the speed of operation and optimises hardware. Compared to existing HFPMs, the proposed HFPM utilises a novel hybrid radix-4/radix-8 booth encoder. The hybrid architecture reduces the computations by an average of k/3 for a k-bit 2’s complement representation by reducing the number of partial products. In addition, to achieve an area-efficient and power-efficient design, approximate computational units are added to the radix-8 booth encoder in the hybrid architecture with a slight reduction in accuracy. The efficiency of the approximate architecture is measured in scales of Error Rate (ER) and Normalized Error Distance (NED). The proposed design is implemented on Kintex 7 FPGA and realized on 45nm ASIC platforms. The experimental study shows that the proposed multiplier has utilised hardware (831 slice LUT, 828 LUT as logic) and consumed 6110 μm2 of area and 83 μW of power which is less as compared to existing floating point multipliers. The experimental results in terms of average Structural Similarity Index Measure (SSIM) is 0.98 which is better than the existing floating point multipliers are compared.

An efficient multi-format low-precision floating-point multiplier

Low-precision computing has emerged as a promising technology to enhance performance in modern applications like deep neural network training and scientific computing. However, most existing circuits and systems are tailored to a single type of half-precision format, such as FP16 or BFloat16. In light of this limitation, this paper introduces the design of a multi-format floating-point multiplier capable of supporting a wide range of half-precision formats, including both their signed and unsigned versions. Our design emphasizes high reconfigurability, allowing it to adapt to the required dynamic range and precision. Moreover, experimental results showed that the introduced unsigned versions of the half-precision floating-point formats resulted in improved circuit parameters and energy consumption.

ApproxTrain: Fast Simulation of Approximate Multipliers for DNN Training and Inference

Edge training of Deep Neural Networks (DNNs) is a desirable goal for continuous learning; however, it is hindered by the enormous computational power required by training. Hardware approximate multipliers have shown their effectiveness in gaining resource-efficiency in DNN inference accelerators; however, training with approximate multipliers is largely unexplored. To build resource-efficient accelerators with approximate multipliers supporting DNN training, a thorough evaluation of training convergence and accuracy for different DNN architectures and different approximate multipliers is needed. This paper presents ApproxTrain1, an open-source framework that allows fast evaluation of DNN training and inference using simulated approximate multipliers. ApproxTrain is as user-friendly as TensorFlow (TF) and requires only a high-level description of a DNN architecture along with C/C++ functional models of the approximate multiplier. We improve the speed of the simulation at the multiplier level by using a novel LUT-based approximate floating-point (FP) multiplier simulator on GPU (AMSim). Additionally, a novel flow is presented to seamlessly convert C/C++ functional models of approximate FP multipliers into AMSim. ApproxTrain leverages CUDA and efficiently integrates AMSim into the TensorFlow library to overcome the absence of native hardware approximate multiplier in commercial GPUs. We use ApproxTrain to evaluate the convergence and accuracy performance of DNN training with approximate multipliers for three application domains: image classification, object detection, and neural machine translation. The evaluations demonstrate similar convergence behavior and negligible change in test accuracy compared to FP32 and Bfloat16 multipliers. Compared to CPU-based approximate multiplier simulations in training and inference, the GPU-accelerated ApproxTrain is more than 2500× faster. Based on highly optimized closed-source cuDNN/cuBLAS libraries with native hardware multipliers, the original TensorFlow is, on average, only 8× faster than ApproxTrain.

Comparative study of single precision floating point division using different computational algorithms

<span>This paper presents different computational algorithms to implement single precision floating point division on field programmable gate arrays (FPGA). Fast division computation algorithms can apply to all division cases by which an efficient result will be obtained in terms of delay time and power consumption. 24-bit Vedic multiplication (Urdhva-Triyakbhyam-sutra) technique enhances the computational speed of the mantissa module and this module is used to design a 32-bit floating point multiplier which is the crucial feature of this proposed design, which yields a higher computational speed and reduced delay time. The proposed design of floating-point divider using fast computational algorithms synthesized using Verilog hardware description language has a 32-bit floating point multiplier module unit and a 32-bit floating point subtractor module unit. Xilinx Spartan 6 SP605 evaluation platform is used to verify this proposed design on FPGA. Synthesis results provide the device utilization and propagation delay parameters for the proposed design and a comparative study is done with previous work. Input to the divider is provided in IEEE 754 32-bit formats.</span>

Development of floating point operating devices

The paper shows a well-known approach to the construction of cores in multi-core microprocessors, which is based on the application of a data flow graph-driven calculation model. The architecture of such kernels is based on the application of the reduced instruction set level data flow model proposed by Yale Patt. The object of research is a model of calculations based on data flow management in a multi-core microprocessor. The results of the floating-point multiplier development that can be dynamically reconfigured to handle five different formats of floating-point operands and an approach to the construction of an operating device for addition-subtraction of a sequence of floating-point numbers are presented, for which the law of associativity is fulfilled without additional programming complications. On the basis of the developed circuit of the floating-point multiplier, it is possible to implement various variants of the high-speed multiplier with both fixed and floating points, which may find commercial application. By adding memory elements to each of the multiplier segments, it is possible to get options for building very fast pipeline multipliers. The multiplier scheme has a limitation: the exponent is not evaluated for denormalized operands, but the standard for floating-point arithmetic does not require that denormalized operands be handled. In such cases, the multiplier packs infinity as the result. The implementation of an inter-core operating device of a floating-point adder-subtractor can be considered as a new approach to the practical solution of dynamic planning tasks when performing addition-subtraction operations within the framework of a multi-core microprocessor. The limitations of its implementation are related to the large amount of hardware costs required for implementation. To assess this complexity, an assessment of the value of the bits of its main blocks for various formats of representing floating-point numbers, in accordance with the floating-point standard, was carried out.

An Approach to the Implementation of a Neural Network for Cryptographic Protection of Data Transmission at UAV

An approach to the implementation of a neural network for real-time cryptographic data protection with symmetric keys oriented on embedded systems is presented. This approach is valuable, especially for onboard communication systems in unmanned aerial vehicles (UAV), because of its suitability for hardware implementation. In this study, we evaluate the possibility of building such a system in hardware implementation at FPGA. Onboard implementation-oriented information technology of real-time neuro-like cryptographic data protection with symmetric keys (masking codes, neural network architecture, and matrix of weighting coefficients) has been developed. Due to the pre-calculation of matrices of weighting coefficients and tables of macro-partial products and the use of tabular-algorithmic implementation of neuro-like elements and dynamic change of keys, it provides increased cryptographic stability and hardware–software implementation on FPGA. The table-algorithmic method of calculating the scalar product has been improved. By bringing the weighting coefficients to the greatest common order, pre-computing the tables of macro-partial products, and using operations of memory read, fixed-point addition, and shift operations instead of floating-point multiplication and addition operations, it provides a reduction in hardware costs for its implementation and calculation time as well. Using a processor core supplemented with specialized hardware modules for calculating the scalar product, a system of neural network cryptographic data protection in real-time has been developed, which, due to the combination of universal and specialized approaches, software, and hardware, ensures the effective implementation of neuro-like algorithms for cryptographic encryption and decryption of data in real-time. The specialized hardware for neural network cryptographic data encryption was developed using VHDL for equipment programming in the Quartus II development environment ver. 13.1 and the appropriate libraries and implemented on the basis of the FPGA EP3C16F484C6 Cyclone III family, and it requires 3053 logic elements and 745 registers. The execution time of exclusively software realization of NN cryptographic data encryption procedure using a NanoPi Duo microcomputer based on the Allwinner Cortex-A7 H2+ SoC was about 20 ms. The hardware–software implementation of the encryption, taking into account the pre-calculations and settings, requires about 1 msec, including hardware encryption on the FPGA of four 2-bit inputs, which is performed in 160 nanoseconds.

On the Design of Iterative Approximate Floating-Point Multipliers

approximate multipliers provide power and area-saving for error-resilient applications. In this paper, we first propose two approximate floating-point multipliers based on two-dimensional pseudo-Booth encoding: floating-point pseudo-Booth (PB), and floating-point iterative pseudo-Booth (IPB). The accuracy of proposed multipliers can be tuned by three parameters: iteration, encoder's radix (R), and word length after truncation (W). Next, we developed the conventional iterative multipliers with a simplified steering circuit for their correction part to eliminate the power consumption of multipliers. The proposed iterative multipliers are compared with conventional iterative integer multipliers implemented by a simplified steering circuit for the floating-point area. The results reveal that the proposed PB-R4-W4 and IPB-R16-W19, compared to the exact floating-point multiplier, provide up to 98.9% and 67.5% reductions in power consumption, respectively, in TSMC 180nm CMOS technology. Also, their MRED values are, respectively, 2.9% and ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$7.4\times10^{-4}$</tex-math></inline-formula> )%. Finally, we evaluated the functionality of the proposed multipliers for real-life applications, including a hyper-plane classifier and two image processing applications of smoothing and sharpening.

50-GFLOPS Floating-Point Adder and Multiplier Using Gate-Level-Pipelined Single-Flux-Quantum Logic With Frequency-Increased Clock Distribution

We demonstrate the functioning of a highthroughput, gate-level-pipelined floating-point adder and multiplier over 50 GHz. The gate-level-pipelined floating-point adder and multiplier requires dedicated circuit blocks to wait until other circuit blocks complete calculations because of the dependency between their sign, exponent, and significand parts. We revealed that the resultant delay difference of the waiting circuit blocks hinders high-frequency operation if the pre-designed circuit blocks with the fixed clock distribution are connected in a simple manner. We showed that clock distribution needs to synchronize with every pipeline stage regardless of the circuit blocks to minimize the delay difference between the circuit blocks for circuits containing the waiting circuit blocks (e.g., the floatingpoint adder and multiplier). We designed a 5-bit floating-point adder and multiplier to demonstrate the effectiveness of the clock distribution experimentally. The test chips were fabricated using AIST 10-kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> Advanced Process 2. We verified the highspeed operation at over 50 GHz in the floating-point adder and multiplier. The maximum clock frequency and throughput of the floating-point adder were 56 GHz and 56 GFLOPS, respectively. The corresponding values for the floating-point multiplier were 63 GHz and 63 GFLOPS, respectively.

An area-delay efficient single-precision floating-point multiplier for VLSI systems

The floating-point multiplier (FPM) is the most commonly used component in various image and signal processing applications. An area-delay efficient FPM design could be helpful for the development of high-performance VLSI computing systems. Therefore, this paper presents the analysis of single-precision FPM to find the possibilities for the reduction in delay and area. From the analysis, it is found that the delay of FPM depends on the delay of mantissa multiplication and exponent normalization units. Based on the above observations, in this paper, the delay and area efficient mantissa multiplication and exponent addition-cum-normalization units are proposed. Further, using these components, the single-precision FPM structure is proposed. Synthesis results show that the proposed FPM design offers a saving of 15.3% in delay and 10.8% in area compared to the best available existing FPM design. Besides, the proposed FPM consumes 13.0% less power-delay-product and involves 24.4% less area-delay-product in comparison to the best available existing design. Finally, effectiveness of the proposed single precision floating-point multiplier is presented in Gaussian smoothing filter of the image processing application.

Finding Normal Binary Floating-Point Factors Efficiently

Solving the floating-point equation x otimes y = z, where x, y and z belong to floating-point intervals, is a common task in automated reasoning for which no efficient algorithm is known in general. We show that it can be solved by computing a constant number of floating-point factors, and give a fast algorithm for computing successive normal floating-point factors of normal floating-point numbers in radix 2. This leads to an efficient procedure for solving the given equation, running in time of the same order as floating-point multiplication.

Acceleration of Nuclear Reactor Simulation and Uncertainty Quantification Using Low-Precision Arithmetic

In recent years, interest in approximate computing has been increasing significantly in many disciplines in the context of saving energy and computation cost by trading off on the quality of numerical simulation. The hardware acceleration based on the low-precision floating-point arithmetic is anticipated by the upcoming generation of microprocessors and code compilers and has already proven to be beneficial for weather and climate modelling and neural network training. The present work illustrates the application of low-precision arithmetic for the nuclear reactor core uncertainty analysis. We studied the performance of an elementary transient reactor core model for the arbitrary precision of the floating-point multiplication in a direct linear system solver. Using this model, we calculated the reactor core transients initiated by the control rod ejection taking into account the uncertainty of the model input parameters. Then, we evaluated the round-off errors of the model outputs for different precision levels. The comparison of the round-off errors and the model uncertainty showed the model could be run using a 15-bit floating-point number precision with an acceptable degradation of the result’s accuracy. This precision corresponds to a gain of about 6× in the bit complexity of the linear system solution algorithm, which can be actualized in terms of reduced energy costs on low-precision hardware.

IMPLEMENTATION OF HIGH PERFORMANCE POSIT-MULTIPLIER

To represent real numbers, practically all computer systems now employ IEEE-754 floating point. Posit has recently been offered as an alternative to IEEE-754 floating point because it provides higher accuracy and a wider dynamic range. The use of not-a-numbers (NaN's) is one of the most common , having too many of them wastes valuable bit patterns in floating point format. As an alternative to floating point, a system known as "Universal Numbers'' or UNUMs was developed. There are three variations of this system, but in terms of hardware compatibility, Type III(POSIT) is the best substitute for floating point. By employing only one bit pattern, this approach overcomes the NaN problem associated with floating point format. An IEEE float FPU requires 22.2% more circuitry than a posit processing unit. The proposed posit multiplier consumes 28.5% less power compared to corresponding IEEE Floating point format. The number of posit operations per second(POPS) handled by a device can be ubstantially larger than the number of FLOPS due to lower power consumption. In this paper, High performance Posit multiplier is implemented and compared with normal Floating point multiplier.

Floating Point Calculation of the Cube Function on FPGAs

Specialized arithmetic units allow fast and efficient computation of lesser used mathematical functions. The overall impact of those units would be negligible in a general purpose processor, as added circuitry makes chips more complex despite most software would seldom make use of it. On the opposite side, custom computing machines are built for a specific task, and they can always benefit from specialized units if they are available. In this work, floating point architectures are proposed for computing the cube on Intel and Xilinx FPGAs. Those implementations reduce the cost and latency compared to using simple floating point multiplications and squarers.

Design and optimization of MSI-enabled multi-precision binary multiplier architecture

Arithmetic Logic Units (ALUs) are key elements within processors, executing a variety of operations including multiplication, division, addition, and subtraction. Among these, multiplication stands out as the most frequently utilized function within ALUs. This study presents an innovative MSI-interfaced multiplier architecture designed for integration into a multi-precision floating-point multiplier framework. This novel architecture offers configurations for 24-bit, 53-bit, 113-bit, and 237-bit binary operations, corresponding to single, double, quadruple, and octuple precision modes of floating-point computation. Notably, it enhances throughput by accommodating the multiplication of multiple batches of inputs with each operation initiation, surpassing existing binary multiplication systems. A unique Mantissa Similarity Investigation (MSI) implementation is developed and integrated into the binary multiplier architecture. Comparative analysis of the path delay in 24-bit mode against existing 24-bit multipliers demonstrates that the novel MSI-interfaced binary multiplier architecture, with and without MSI, exhibits reduced path delay compared to all existing systems, as anticipated.

FPGA Implementation of Double Precision Floating Point Multiplier

High speed computation is the need of today’s generation of Processors. To accomplish this major task, many functions are implemented inside the hardware of the processor rather than having software computing the same task. Majority of the operations which the processor executes are Arithmetic operations which are widely used in many applications that require heavy mathematical operations such as scientific calculations, image and signal processing. Especially in the field of signal processing, multiplication division operation is widely used in many applications. The major issue with these operations in hardware is that much iteration is required which results in slow operation while fast algorithms require complex computations within each cycle. The result of a Division operation results in a either in Quotient and Remainder or a Floating point number which is the major reason to make it more complex than Multiplication operation.

Optimization of Power and Area Using VLSI Implementation of MAC Unit Based on Additive Multiply Module

The development of Digital Signal Processors (DSPs), graphical systems, Field Programmable Gate Arrays (FPGAs)/ Application-Specific Integrated Circuits (ASICs), and multimedia systems all rely heavily on digital circuits. The need for high-precision fixed-point or floating-point multipliers suitable for Very Large-Scale Integration (VLSI) implementation in high-speed DSP applications is developing rapidly. An integral part of any digital system is the multiplier. In digital systems as well as signal processing, the adder and multiplier seem to be the fundamental arithmetic units. Problems arise when using a multiplier in the realms of area, power, complexity, and speed. This paper details a more efficient MAC (Multiply- Accumulate) multiplier that has been tuned for space usage. The proposed design is more efficient, takes up less room, and has lower latency than conventional designs. The performance of the Additive Multiply Module (AMM) multiplier is measured against that of existing multipliers, where it serves as a module in the MAC reducing area and delay.

Small Logarithmic Floating-Point Multiplier Based on FPGA and Its Application on MobileNet

The small floating-point (SFP) multiplier proposed by Xilinx is utilized to implement the convolution neural networks (CNNs). This scheme can balance the resource usage of look-up tables (LUTs) and digital signal processing blocks (DSPs) so that high compute density is achieved on Field Programmable Gate Arrays (FPGAs). In addition, this scheme can quantize the CNNs with several simple scaling operations rather than a lengthy compute intensive retraining process. However, the mantissa field of SFP multiplier is required to be less than or equal to 3-bit, thus significantly restricts the application of this scheme. To figure out this issue, we implement the SFP multiplier in the logarithmic domain such that the multiplication is performed by the addition with the aid of logarithmic and anti-logarithmic converters that is referred to as small logarithmic floating-point (SLFP) multiplier. Compared to SFP multiplier (3-bit mantissa), the proposed SLFP multiplier can support multiple accuracy levels ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\mathbf {\mathrm {\sim }}5$ </tex-math></inline-formula> -bit mantissa) with a relatively low overhead ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0\mathbf {\mathrm {\sim }} 3\mathbf {\times }$ </tex-math></inline-formula> LUT6s). Moreover, we utilize the look-ahead carry chain to reduce the delay of addition so that the proposed SLFP multiplier can operate at 650MHz. As a result, the latency (1.5ns, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1\mathbf {\times }$ </tex-math></inline-formula> clock cycle) and throughput (650MOPS) of proposed SLFP multiplier ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\mathbf {\mathrm {\sim }}5$ </tex-math></inline-formula> -bit mantissa) are the same as the SFP multiplier (3-bit mantissa). In the end, the implementation of MobileNet proves that the accuracy level of SFP multiplier (3-bit mantissa) is not sufficient, which can be solved by the proposed SLFP multipliers (5-bit mantissa).

Dendrocentric learning for synthetic intelligence.

Artificial intelligence now advances by performing twice as many floating-point multiplications every two months, but the semiconductor industry tiles twice as many multipliers on a chip every two years. Moreover, the returns from tiling these multipliers ever more densely now diminish because signals must travel relatively farther and farther. Although travel can be shortened by stacking tiled multipliers in a three-dimensional chip, such a solution acutely reduces the available surface area for dissipating heat. Here I propose to transcend this three-dimensional thermal constraint by moving away from learning with synapses to learning with dendrites. Synaptic inputs are not weighted precisely but rather ordered meticulously along a short stretch of dendrite, termed dendrocentric learning. With the help of a computational model of a dendrite and a conceptual model of a ferroelectric device that emulates it, I illustrate how dendrocentric learning artificial intelligence-or synthetic intelligence for short-could run not with megawatts in the cloud but rather with watts on a smartphone.

PAM: A Piecewise-Linearly-Approximated Floating-Point Multiplier With Unbiasedness and Configurability

Approximate computing is a promising alternative to improve energy efficiency for IoT devices on the edge. This work proposes a piecewise-linearly-approximated and unbiased floating-point approximate multiplier with run-time configurability. We provide a theoretically sound formulation that turns multiplication approximation to an optimization problem. With the formulation and findings, a multi-level architecture is proposed to easily incorporate run-time configurability and module execution parallelism. Finally, the proposed multiplier is further optimized to reduce the circuit implementation complexity, making the multiplier linearly dependent on the precision requirement, instead of quadratically or exponentially as in prior work. When compared to the prior state-of-the-art approximate floating-point multiplier, ApproxLP M. Imani <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">et al</i> , “ApproxLP: Approximate multiplication with linearization and iterative error control,” in <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Proc. ACM/IEEE Des. Autom. Conf.</i> , 2019, pp. 1–6., the proposed multiplier outperforms in all the aspects including accuracy, area, and delay. By replacing a full-precision floating-point multiplier in GPU, the proposed design can improve the energy efficiency for various edge computing tasks. Even with Level 1 approximation, the proposed multiplier improves energy efficiency up to 20× for machine learning on CIFAR-10, with almost negligible accuracy loss.