Floating-point Expressions Research Articles

Symbolic testing of floating-point bugs and exceptions

Numerical software are susceptible to floating-point bugs and exceptions, which may lead to severe threats like denial of service attacks. Static analysis techniques such as symbolic execution are effective in detecting general bugs which often cause memory error or program crash. Unfortunately, these methods do not deal well with numerical code as they do not support floating-point constraints and math functions symbolically. In this paper, we propose a new analysis framework YUSE, which can detect floating-point bugs by constructing constraints and exploring paths which contain floating-point expressions. Specifically, we introduce interval computation and interval constraint propagation in non-relational numerical abstract domains, and symbolically model math functions, to accurately detect floating-point bugs and exceptions. Moreover, we leverage two-phase constraint solving to enhance YUSE’s performance. Experimental results show that YUSE outperforms two state-of-the-art tools, Frama-c and Fpse-study, in terms of effectiveness and efficiency, with 1.4× and 7.1× faster than Frama-c and Fpse-study, respectively. Moreover, YUSE found 20 new bugs in real-world software, 12 of which were assigned CVE IDs and 8 of which were confirmed by developers.

Detecting Floating-Point Expression Errors Based Improved PSO Algorithm

The use of floating-point numbers inevitably leads to inaccurate results and, in certain cases, significant program failures. Detecting floating-point errors is critical to ensuring that floating-point programs outputs are proper. However, due to the sparsity of floating-point errors, only a limited number of inputs can cause significant floating-point errors, and determining how to detect these inputs and to selecting the appropriate search technique is critical to detecting significant errors. This paper proposes characteristic particle swarm optimization (CPSO) algorithm based on particle swarm optimization (PSO) algorithm. The floating-point expression error detection tool PSOED is implemented, which can detect significant errors in floating-point arithmetic expressions and provide corresponding input. The method presented in this paper is based on two insights: (1) treating floating-point error detection as a search problem and selecting reliable heuristic search strategies to solve the problem; (2) fully utilizing the error distribution laws of expressions and the distribution characteristics of floating-point numbers to guide the search space generation and improve the search efficiency. This paper selects 28 expressions from the FPBench standard set as test cases, uses PSOED to detect the maximum error of the expressions, and compares them to the current dynamic error detection tools S3FP and Herbie. PSOED detects the maximum error 100% better than S3FP, 68% better than Herbie, and 14% equivalent to Herbie. The results of the experiments indicate that PSOED can detect significant floating-point expression errors.

Identifying volatile numeric expressions in numeric computing applications

The results of numerical computations with floating point numbers depend on the execution platform, which we define as the hardware and the tools (compilers, etc.) supporting that hardware. One reason for the dependence is that compilers have significant freedom in deciding how to evaluate a floating point expression, as such evaluation is not standardized (not even in standards such as IEEE-754). Another reason is that hardware may or may not provide specialized instructions like Fused Multiply Add (FMA), and if it does, the compiler can take advantage of FMA functionality in different ways.We call an expression volatile if, for some input, its value differs across platform parameters. Differences can become particularly large across heterogeneous parallel architectures. This undermines the software portability promised by programming standards such as OpenCL and significantly impacts reproducibility of results in general.In this paper, we present a technique that predicts bounds on the output of a program containing volatile expressions when executed on different platforms. Using randomly selected inputs, we compare the bounds to results from running the code across a variety of platforms including CPUs and GPUs. Our results show that the theoretical bounds are relatively tight (within an order of magnitude) and can help users pinpoint where results should be stabilized, for instance by restricting expression reordering.

Efficient automated repair of high floating-point errors in numerical libraries

Floating point computation is by nature inexact, and numerical libraries that intensively involve floating-point computations may encounter high floating-point errors. Due to the wide use of numerical libraries, it is highly desired to reduce high floating-point errors in them. Using higher precision will degrade performance and may also introduce extra errors for certain precision-specific operations in numerical libraries. Using mathematical rewriting that mostly focuses on rearranging floating-point expressions or taking Taylor expansions may not fit for reducing high floating-point errors evoked by ill-conditioned problems that are in the nature of the mathematical feature of many numerical programs in numerical libraries. In this paper, we propose a novel approach for efficient automated repair of high floating-point errors in numerical libraries. Our main idea is to make use of the mathematical feature of a numerical program for detecting and reducing high floating-point errors. The key components include a detecting method based on two algorithms for detecting high floating-point errors and a repair method for deriving an approximation of a mathematical function to generate patch to satisfy a given repair criterion. We implement our approach by constructing a new tool called AutoRNP. Our experiments are conducted on 20 numerical programs in GNU Scientific Library (GSL). Experimental results show that our approach can efficiently repair (with 100% accuracy over all randomly sampled points) high floating-point errors for 19 of the 20 numerical programs.

Systematic Design Space Exploration of Floating-Point Expressions on FPGA

In this brief, we propose novel methods to systematically explore the design space of floating-point expressions on a field-programmable gate array in order to extract a nondominated set that covers the whole design space in terms of the accuracy, area, and run-time numbers. We first introduce a regular selection method that consists of two main phases: 1) generating equivalent expressions and 2) using a Pareto algorithm to extract a nondominated set. Then, we introduce a fast selection method in which two phases are composed in order to speed up the optimization process, while the quality of the final results does not change significantly. The results show that regular selection enjoys up to a 35.3% run-time improvement in comparison with the state-of-the-art techniques. Furthermore, the fast selection method is approximately 45× faster than the regular selection.

OptiFEX: A Framework for Exploring Area-Efficient Floating Point Expressions on FPGAs With Optimized Exponent/Mantissa Widths

Field-programmable gate arrays (FPGAs) could outperform microprocessors on floating point computations due to massive parallelism, freedom on the selection of exponent/mantissa width, and utilization of simplified adders and multipliers. However, optimized use of resources and accuracy of the final implemented expression are two important issues in the implementation of floating point arithmetic expressions on FPGAs. High-level optimizations such as changing the form of floating point initial expression by arithmetic rules or deciding on the exponent and mantissa widths have significant effects on the resource usage, accuracy, and efficiency of the final implementation. In this paper, we introduce an optimization framework called OptiFEX, which enables designers to optimize an initial floating point expression in terms of the resource usage and the exponent and mantissa widths based on: 1) input intervals; 2) the smallest presentable number in the implementation; and 3) the maximum permitted error interval provided by the designer. First, we come up with some techniques to generate equivalent expressions for the initial expression, and we make use of some heuristics to speed up the process of equivalent expressions’ generation. We also propose a method to estimate the mantissa width. Finally, we introduce an algorithm to choose the best expressions in terms of the resource usage based on the estimated mantissa and exponent widths.

Automatically improving accuracy for floating point expressions

Scientific and engineering applications depend on floating point arithmetic to approximate real arithmetic. This approximation introduces rounding error, which can accumulate to produce unacceptable results. While the numerical methods literature provides techniques to mitigate rounding error, applying these techniques requires manually rearranging expressions and understanding the finer details of floating point arithmetic. We introduce Herbie, a tool which automatically discovers the rewrites experts perform to improve accuracy. Herbie's heuristic search estimates and localizes rounding error using sampled points (rather than static error analysis), applies a database of rules to generate improvements, takes series expansions, and combines improvements for different input regions. We evaluated Herbie on examples from a classic numerical methods textbook, and found that Herbie was able to improve accuracy on each example, some by up to 60 bits, while imposing a median performance overhead of 40%. Colleagues in machine learning have used Herbie to significantly improve the results of a clustering algorithm, and a mathematical library has accepted two patches generated using Herbie.

Robustness Analysis of Floating-Point Programs by Self-Composition

Robustness is a key property for critical systems that run in uncertain environments, to ensure that small input perturbations can cause only small output changes. Current critical systems often involve lots of floating-point computations which are inexact. Robustness analysis of floating-point programs needs to consider both the uncertain inputs and the inexact computation. In this paper, we propose to leverage the idea of self-composition to transform the robustness analysis problem into a reachability problem, which enables the use of standard reachability analysis techniques such as software model checking and symbolic execution for robustness analysis. To handle floating-point arithmetic, we employ an abstraction that encompasses the effect of rounding and that can encompass all rounding modes. It converts floating-point expressions into linear expressions with interval coefficients in exact real arithmetic. On this basis, we employ interval linear programming to compute the maximum output change or maximum allowed input perturbation for the abstracted programs. Preliminary experimental results of our prototype implementation are encouraging.

Compact FPU Design and Embedding in a Ubiquitous Processor for Multimedia Performance Enhancement

The key to protect huge amount of multimedia data in ubiquitous networks is to introduce safety aware high-performed single VLSI processor systems embedded with cipher process. Thus, we exploited the architecture of a hardware cryptography embedded multimedia mobile processor named HC-gorilla by sophisticatedly unifying up-to-date processor techniques. Although it was provided with carefully selected Java bytecodes and cipher codes, FP (floating point) expression was omitted due to the restriction of hardware resource. Considering recent trend of embedded applications like voice recognition, 3D graphics, and image/vision processing, FP hardware is crucial for further enhancing HCgorillafs Java functions. We focus in this article the development of a compact FPU (Floating point number Processing Unit). A compact FP format speci¯c for HCgorilla is IEEE 754 compatible except the bit width representation of FP data. Prioritizing the latency of FPU, it has only 5 stages. The compact FPU is built in HCgorilla by adding 16 FP arithmetic codes and improving the decode stage of the previous HCgorilla. By using a 0.18-¹m standard cell CMOS technology supported by VDEC, we have so far accomplished the logic synthesis and behavior simulation. The 400MHz of clock frequency is justified from delay analysis.

Programmable gain amplifier with colour balancing for CCD image sensors

The authors present a new programmable gain amplifier (PGA) with colour balancing for single-chip CCD colour image sensors. The PGA with synchronised gain switching allows higher SNR to be achieved in the amplified image while maintaining sufficient gain resolution and low power dissipation. A floating-point expression is used in the designed five-stage pipelined PGA for compact and low-power implementation. Low-noise gain switching with a cross-coupled ring counter sufficiently suppresses the pattern noise due to the high-speed gain switching. The power consumption is 119 mW at 3.3 V supply voltage and 20 MHz pixel rate.