Floating Gate Memory Devices Research Articles

Ultrafast Non-Volatile Floating-Gate Memory Based on All-2D Materials.

The explosive growth of massive-data storage and the demand for ultrafast data processing require innovative memory devices with exceptional performance. 2D materials and their van der Waal heterostructures with atomically sharp interfaces hold great promise for innovations in memory devices. Here, this work presents non-volatile, floating-gate memory devices with all functional layers made of 2D materials, achieving ultrafast programming/erasing speeds (20ns), high extinction ratios (up to 108), and multi-bit storage capability. These devices also exhibit long-term data retention exceeding 10 years, facilitated by a high gate-coupling ratio (GCR) and atomically sharp interfaces between functional layers. Additionally, this work demonstrates the realization of an "OR" logic gate on a single-device unit by synergistic electrical and optical operations. The present results provide a solid foundation for next-generation ultrahigh-speed, ultralong lifespan, non-volatile memory devices, with a potential for scale-up manufacturing and flexible electronics applications.

A 2D Heterostructure-Based Multifunctional Floating Gate Memory Device for Multimodal Reservoir Computing.

The demand for economical and efficient data processing has led to a surge of interest in neuromorphic computing based on emerging two-dimensional (2D) materials in recent years. As a rising van der Waals (vdW) p-type Weyl semiconductor with many intriguing properties, tellurium (Te) has been widely used in advanced electronics/optoelectronics. However, its application in floating gate (FG) memory devices for information processing has never been explored. Herein, an electronic/optoelectronic FG memory device enabled by Te-based 2D vdW heterostructure for multimodal reservoir computing (RC) is reported. When subjected to intense electrical/optical stimuli, the device exhibits impressive nonvolatile electronic memory behaviors including ≈108 extinction ratio, ≈100 ns switching speed, >4000 cycles, >4000-s retention stability, and nonvolatile multibit optoelectronic programmable characteristics. When the input stimuli weaken, the nonvolatile memory degrades into volatile memory. Leveraging these rich nonlinear dynamics, a multimodal RC system with high recognition accuracy of 90.77% for event-type multimodal handwritten digit-recognition is demonstrated.

Atomically engineered, high-speed non-volatile flash memory device exhibiting multibit data storage operations

Non-volatile memory devices, which offer large capacity and mechanical dependability as a mainstream technology, have played a key role in fostering innovation in modern electronics. Despite the advantages of non-volatile memory devices, their low ON/OFF ratio and slow operational speed have limited their performance compared to their volatile counterparts. In this study, we present a non-volatile floating-gate memory device based on van der Waals heterostructures, which exhibits ultrahigh-speed memory operations in the range of a hundred nanoseconds with an extinction ratio of up to 106. The device consists of atomically sharp interfaces between different functional elements, including atomically thin sheet of multilayer Graphene (MGr) as a floating gate, hexagonal boron nitride (h-BN) as a tunnel barrier, and two-dimensional (2D) semiconductor tin di-selenide (SnSe2) as a channel material. The memory device exhibits excellent endurance performance with stable and dependable behavior across numerous program/erase cycles, comparable to commercial volatile dynamic random access memory technology. In addition, we demonstrate the ability of the device to store multiple bits per memory cell, which offers promising potential for ultrahigh-density information storage. Our findings provide important implications for memory storage, data processing, and electronic device development, and offer new opportunities in the field of emerging 2D materials with optimal device engineering.

Double-floating-gate memory device based on energy band engineered van der Waals heterostructure

Floating-gate memory devices based on two-dimensional van der Waals heterostructures are considered as promising candidates for next-generation nonvolatile memories. Here, we report a nonvolatile double-floating-gate (DFG) memory device based on a ReS2/boron nitride/black phosphorus (BP)/boron nitride/graphene heterostructure. By comparing with a single-floating-gate device we fabricated, the device shows enlarged memory window, high on–off ratio, and improved retention performance. Based on these findings, we propose energy band diagrams showing how the memory performance can be improved by energy band engineering through designing the van der Waals heterostructure. In the DFG structure, electrons could transfer between the ReS2 channel and BP as well as between BP and graphene, providing greater controllability for electron tunneling and injection. By choosing graphene and BP as two floating gates, an energy barrier rising from the conduction-band offset between multilayer graphene and BP is set up to efficiently prevent charge leakage from the graphene floating gate and, thus, improve the memory performance. Our work demonstrates an effective way for future designs of high-performance nonvolatile flash memories.

Impact of Interface Traps in Floating-Gate Memory Based on Monolayer MoS

Two-dimensional materials (2DMs) have found potential applications in many areas of electronics, such as sensing, memory systems, optoelectronics, and power. Despite an intense experimental work, the literature is lacking of accurate modeling of nonvolatile memories (NVMs) based on 2DMs. In this work, using technology CAD simulations and model calibration with experiments, we show that the experimental program/erase characteristics of floating-gate (FG) memory devices based on monolayer molybdenum disulphide can be explained by considering bandgap trap states at the dielectric–semiconductor interface. The simulation model includes a classical approach based on drift-diffusion longitudinal channel transport and on nonlocal Wentzel–Kramers–Brillouin (WKB) tunneling for transversal transport (responsible of FG charging/discharging) and for tunneling at contacts. From hysteresis and pulse programming simulations on scaled devices, we find that the long-channel programming window is still maintained at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim 100$ </tex-math></inline-formula> nm and that process improvements aimed at reducing the concentration of interface traps in the semiconducting bandgap could significantly optimize memory operation.

An Overturned Charge Injection Synaptic Transistor With a Floating-Gate for Neuromorphic Hardware Computing

An overturned charge injection synaptic transistor (OCIST) is experimentally demonstrated for neuromorphic hardware computing. The structure of the OCIST is similar to that of a conventional floating gate memory except for the directionality of charge injection. The charge valve layer (CVL) of the OCIST is analogous to a blocking oxide of a floating gate memory device. The OCIST employs the CVL to control charge flow to the floating gate, while the floating gate memory utilizes a tunneling oxide as a gate oxide for this. Because the CVL and the gate oxide are decoupled in the OCIST, the CVL is independently engineerable without any sacrifice of the gate oxide quality and scalability. Moreover, the selection spectrum for the CVL material is wide. Linearity and symmetry of synaptic potentiation and depression were improved. In addition, a classification accuracy of 92.4% for handwritten digits in the MNIST dataset was achieved.

Sub-femto-Joule energy consumption memory device based on van der Waals heterostructure for in-memory computing

In-memory computing has carried out calculations in situ within each memory unit and its main power consumption comes from data writing and erasing. Further improvements in the energy efficiency of in-memory computing require memory devices with sub-femto-Joule energy consumption. Floating gate memory devices based on two-dimensional (2D) material heterostructures have outstanding characteristics such as non-volatility, multi-bit storage, and low operation energy, suitable for application in in-memory computing chips. Here, we report a floating gate memory device based on a WSe2/h-BN/Multilayer-graphene/h-BN heterostructure, the energy consumption of which is in sub-femto Joule (0.6 fJ) per operation for program/erase, and the read power consumption is in the tens of femto Watt (60 fW) range. We show a Hopfield neural network composed of WSe2/h-BN/Multilayer-graphene/h-BN heterostructure floating gate memory devices, which can recall the original patterns from incorrect patterns. These results shed light on the development of future compact and energy-efficient hardware for in-memory computing systems.

A Steep-Slope Phenomenon by Gate Charge Pumping in a MOSFET

A steep-slope phenomenon is experimentally demonstrated and analyzed with a novel FET referred to as a charge pump FET (CP-FET) by using transient switching of the floating gate voltage. It is also analytically modeled and verified by simulation. The CP-FET, which is very similar to a flash memory cell structure composed of a floating gate, was fabricated with 100 % CMOS microfabrication. The transition layer in the CP-FET is analogous to a blocking oxide in a floating gate memory device. Transient switching of the floating gate voltage is achieved by two factors. One is capacitance mismatching between a control gate and the floating gate, which is realized by designing the area of the transition layer to be smaller than that of the floating gate. The other is charge pumping to the floating gate by use of the current flowing through the transition layer.

Atomically sharp interface enabled ultrahigh-speed non-volatile memory devices.

The development of high-performance memory devices has played a key role in the innovation of modern electronics. Non-volatile memory devices have manifested high capacity and mechanical reliability as a mainstream technology; however, their performance has been hampered by low extinction ratio and slow operational speed. Despite substantial efforts to improve these characteristics, typical write times of hundreds of micro- or milliseconds remain a few orders of magnitude longer than that of their volatile counterparts. Here we demonstrate non-volatile, floating-gate memory devices based on van der Waals heterostructures with atomically sharp interfaces between different functional elements, achieving ultrahigh-speed programming/erasing operations in the range of nanoseconds with extinction ratio up to 1010. This enhanced performance enables new device capabilities such as multi-bit storage, thus opening up applications in the realm of modern nanoelectronics and offering future fabrication guidelines for device scale up.

Newly Synthesized Nonvacuum Processed High‐k Polymeric Dielectrics with Carboxyl Functionality for Highly Stable Operating Printed Transistor Applications

AbstractSolution‐processed polar hydroxyl containing polymers such as poly(4‐vinylphenol) are widely utilized in organic filed‐effect transistors (OFETs) due to their high dielectric constant (k) and excellent insulating properties owing to the crosslinking through their hydroxyl groups. However, hydroxyl functionalities can function as trapsites, and their crosslinking reactions decrease the k value of materials. Hence, in this study, new solution‐processable copolymers containing both carboxyl and hydrophobic functionalities are synthesized. A fluorophenyl azide (FPA) based UV‐assisted crosslinker is also employed to promote the movement of polar carboxyl groups toward the bulk region and the hydrophobic functionalities to the surface region, thereby maintaining the high‐k characteristics and hydrophobic surface in thin film. Thus, the addition of an FPA crosslinker eliminates the trapsites on the surface, allowing a stable operation and efficient charge transport. Additionally, the solution‐processability enables the production of uniform and thin films to yield OFETs with stable and low‐voltage driving characteristics. The printed layers are also applied as gate dielectrics for floating gate memory devices and in integrated one‐transistor‐one‐transistor based memory cells, displaying their excellent memory performance. The synthesis and fabrication strategies employed in this study can become useful guidelines for the production of high‐k dielectrics for stable OFETs and other applications.

A low-power biomimetic collision detector based on an in-memory molybdenum disulfide photodetector

Accurately detecting a potential collision and triggering a timely escape response is critical in the field of robotics and autonomous vehicle safety. The lobula giant movement detector (LGMD) neuron in locusts can detect an approaching object and prevent collisions within a swarm of millions of locusts. This single neuronal cell performs nonlinear mathematical operations on visual stimuli to elicit an escape response with minimal energy expenditure. Collision avoidance models based on image processing algorithms have been implemented using analogue very-large-scale-integration designs, but none is as efficient as this neuron in terms of energy consumption or size. Here we report a nanoscale collision detector that mimics the escape response of the LGMD neuron. The detector comprises a monolayer molybdenum disulfide photodetector stacked on top of a non-volatile and programmable floating-gate memory architecture. It consumes a small amount of energy (in the range of nanojoules) and has a small device footprint (~1 µm × 5 µm). By integrating a MoS2 photodetector with a floating-gate memory device, a nanoscale collision detector can be created that mimics the escape response of the lobula giant movement detector neuron.

Well-ordered nanoparticle arrays for floating gate memory applications

A non-volatile floating gate memory device containing well-ordered Au nanoparticles (NPs) is fabricated as a metal–oxide–semiconductor capacitor structure. With superior control on the size, shape and position of nanoparticles, the presented nano-floating gate memory (NFGM) device possesses almost perfect precision of device geometry. The well-ordered Au NPs embedded within the memory device exhibit large memory window at low operation voltages (8.8V @ ± 15V), fast operation time (<10−4 s) and good retention (up to 107 s). In this work, the structural properties of the NFGM device are correlated with the examined electrical properties. The current results are compared with the other studies in the literature to emphasis the advantages of the precise ordering and geometry of the NPs.

Memristive and CMOS Devices for Neuromorphic Computing.

Neuromorphic computing has emerged as one of the most promising paradigms to overcome the limitations of von Neumann architecture of conventional digital processors. The aim of neuromorphic computing is to faithfully reproduce the computing processes in the human brain, thus paralleling its outstanding energy efficiency and compactness. Toward this goal, however, some major challenges have to be faced. Since the brain processes information by high-density neural networks with ultra-low power consumption, novel device concepts combining high scalability, low-power operation, and advanced computing functionality must be developed. This work provides an overview of the most promising device concepts in neuromorphic computing including complementary metal-oxide semiconductor (CMOS) and memristive technologies. First, the physics and operation of CMOS-based floating-gate memory devices in artificial neural networks will be addressed. Then, several memristive concepts will be reviewed and discussed for applications in deep neural network and spiking neural network architectures. Finally, the main technology challenges and perspectives of neuromorphic computing will be discussed.

Multi-level flash memory device based on stacked anisotropic ReS2-boron nitride-graphene heterostructures.

Charge-trapping memory devices based on two-dimensional (2D) material heterostructures possess an atomically thin structure and excellent charge transport capability, making them promising candidates for next-generation flash memories to achieve miniaturized size, high storage capacity, fast switch speed, and low power consumption. Here, we report a nonvolatile floating-gate memory device based on an ReS2/boron nitride/graphene heterostructure. The implemented ReS2 memory device displays a large memory window exceeding 100 V, leading to an ultrahigh current ratio over 108 between programming and erasing states. The ReS2 memory device also exhibits an ultrafast switch speed of 1 μs. In addition, the device can endure hundreds of switching cycles and shows stable retention characteristics with ∼40% charge remaining after 10 years. More importantly, taking advantage of its anisotropic electrical properties, a single ReS2 flake can achieve direction-sensitive multi-level data storage to enhance the data storage density. On the basis of these characteristics, the proposed ReS2 memory device is potentially able to serve the entire memory device hierarchy, meeting the need for scalability, capacity, speed, retention, and endurance at each level.

Scaling down of cobalt quantum‐dots by colloidal route for non‐volatile memory device application

The present work details the synthesis of cobalt quantum-dots (Co QDs) with size downscaling to 1–2 nm and their applications in non-volatile memory (NVM) devices. The process of colloidal synthesis is simple and provides the control over a wide range of QDs size. The scaled-down colloidal Co QDs are applied for the NVM device fabrication. Colloidal synthesised Co QDs are spin-coated over silicon dioxide wafer for the fabrication of floating-gate NVM devices. Capacitance–voltage (C–V) and capacitance–time (C–t) measurements of the fabricated NVM device indicate a low voltage operation of device. A sweep voltages as small as 1.2–4 V lead to a flat band voltage shift of 0.35–1.5 V, evidencing the low operating voltage and low power NVM applications. Further, retention characteristics show a robust retention by fabricated NVM device. In addition, C–V measurements are done for the several samples in order to study the process repeatability. The work also is compared with the other processes for the floating gate memory device.

Multilevel MoS2 Optical Memory with Photoresponsive Top Floating Gates.

Optoelectronic memory devices, whose states can be controlled using electrical optical signals, are receiving much attention for their potential applications in image sensing and parallel data transmission and processes. Here, we report MoS2-based devices with top floating gates of Au, graphene, and MoS2. Unlike conventional floating gate memory devices, our devices have the photoresponsive floating gate at the top, acting as a charge trapping layer. Stable and reliable switching with an on/off ratio of ∼106 and a retention time of >104 s is achieved by illumination with 405 nm light pulses as well as application of gate voltage pulses. However, upon illumination with 532 or 635 nm light pulses, multilevel optical memory effects are observed, which are dependent on the wavelength and the optical exposure dosage. In addition, compared to the device employing a graphene floating gate, the device with an MoS2 floating gate is more sensitive to light, suggesting that the multilevel optical memory properties originate from photoexcited carriers in the top floating gate and can be modulated by adjusting the top floating gate materials. The structure of the top floating gate may open up a new way to novel optoelectronic memory devices.

Characterization of floating-gate memory device with thiolate-protected gold and gold-palladium nanoclusters

The floating-gate memory characteristics of thiolate-protected gold (Au:SR) and palladium doped Au (AuPd:SR) nanoclusters, Au25(SR)18, Au24Pd(SR)18, and Au38(SR)24 (R = C12H25), were investigated by capacitance-voltage (C–V) measurements in vacuum. Monolayer films of Au:SR nanoclusters were formed as floating-gate memory layers on p-type Si substrates by the Langmuir-Schaefer method with surface pressure − area (π-A) isotherm measurements. A fluoropolymer (CYTOP, ∼15 nm thick) was spin-coated on top to form a hydrophobic insulating layer. Using an Au pad (∼40 nm thick) as the gate electrode, C–V measurements exhibit clockwise hysteresis curves originating from the Au:SR and AuPd:SR nanoclusters against the reference measured in each sample, and the hysteresis widths were dependent on the composition and sizes of the Au:SR nanoclusters. The positive and negative voltage shifts in the hysteresis can be explained in terms of electronic structures in Au:SR and AuPd:SR-based devices.

High-Performance Nonvolatile Organic Transistor Memory Using Quantum Dots-Based Floating Gate

A novel nonvolatile floating-gate transistor memory device using CdSe@ZnS quantum dots (QDs) embedded the insulating polymer as a charge-storage layer along with the rational design of device structure is presented. The core-shell structure CdSe@ZnS QDs can efficiently trap both holes and electrons under the applied writing/erasing operations, resulting in a considerable threshold voltage shifts (ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ) over 50 V and forming high-conductance (ON) and low-conductance (OFF) states at a gate voltage of 0 V. The value of threshold voltage shift is controlled by writing and erasing voltages, regardless with source-drain voltages. Furthermore, it exhibits a long retention time (the ΔV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> can maintain 76% at 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> s) and outstanding endurance characteristics (>500 cycles), demonstrating extraordinary stable and reliable memory property. Moreover, a thin layer of Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> was introduced as tunneling dielectric layer which is essential for the high-performance floating-gate transistor memory device. The nonvolatile organic transistor memory devices using QDs-based floating gate show great potential application for high-performance organic memory devices.

A Timeline for Flash Memory History [The Art of Storage

At the annual Flash Memory Summits, we have shown an everexpanding timeline for the history of flash memory, starting in 1967 with the invention of the floating gate memory device by Kahng and Sze of Bell Labs (Figure 1). The timeline now goes out to midyear 2016. We include this timeline with this article to illustrate the development of this key storage technology for many consumer devices. Jim Handy, Brian Berg, and Tom Coughlin put together this ever-growing timeline of advances in solid-state memory and its applications.

Investigation of impact of post-metallization annealing on reliability of 65 nm NOR floating-gate flash memories

This paper investigates the impact of post-metallization annealing (PMA) in pure nitrogen ambient on the reliability of 65nm NOR-type floating-gate flash memory devices. The experimental results show that, with PMA process, the cycling performance of flash cells, especially for the erasing speed is obviously degraded compared to that without PMA. It is found that the bulk oxide traps and tunnel oxide/Si interface traps are significantly increased with PMA treatment. The water/moisture residues left in the interlayer dielectric layers diffuse to tunnel oxide during PMA process is considered to be responsible for these traps generation, which further enhances the degradation of erase performance. Skipping PMA treatment is proposed to suppress the water diffusion effect on erase performance degradation of flash cells.