Floating-gate Inverters Research Articles

High speed column-parallel CDS/ADC circuit with nonlinearity compensation for CMOS image sensors

A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper. The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a three-phase column-parallel circuit based on two floating gate inverters and switched-capacitor network. The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step. A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step, which can reduce the clock step from 2 n to 2(n/2+1). The floating gate inverters are implemented to reduce the power consumption. Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter, which can equalize the coupling path in three phases of the proposed circuit. This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18 μm process. Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10 MHz. The power consumption of this circuit is less than 36.5 μW with a 3.3 V power supply. The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.

Extracción de parámetros eléctricos de inversores CMOS de compuerta flotante

This work provides an accurate methodology for extracting the floating-gate gain factor g, of CMOS floating-gate inverters with a clock-driven switch for accessing temporarilly to the floating-gate. With the methodology proposed in this paper, the g factor and other parasiticcapacitances coupled to the floating-gate can be easily extracted in a mismatch-free approach. This parameter plays animportant role in modern analog and mixed-signal CMOS circuits, since it limits the circuit performance. Theoretical and measured values using two test cells, fabricated in a standard double poly double metal CMOS AMI-ABN process with 1.2mm design rules, were compared. The extracted parameters can be incorporated into floating-gate PS pice macromodels for obtaining accurate electrical simulation.

Operating Margin-Oriented Design Methods for Threshold Element-Based Reconfigurable Logic Circuits Realizing any Symmetric Function

This paper presents operating margin-oriented design methods for threshold element-based reconfigurable logic circuits (TREC) that can realize any symmetric function. The methods can generate circuits under restrictions that originate in electric and structural properties of physical threshold elements. The threshold element is implemented in a floating-gate circuit that calculates its weighted sum using the charge in the floating gate. The operating margins of the floating-gate circuit are an important factor for its reliable operation because of the use of multiple levels on the charge for the weighted sum. The proposed methods have the three main features. First, the methods guarantee that any symmetric function can always be realized independent of the number of input variables. A designed TREC comprising (k + 2) floating-gate inverters realizes one of 2(k + 1) symmetric functions of k input variables, using binary (k + 1) control variables. Secondly, a unique circuit structure is determined by selecting the proper values for the parameters that characterize the floating-gate inverters. These values maximize the operating margins against variations and fluctuations in both the charge and the floating-gate threshold voltage. Lastly, the operating margins are illustrated with a graphical representation. We can obtain knowledge not only of the relationship between the margins, but also of the design trade-off between circuit performances and the margins for reliable operation. To demonstrate the effectiveness of the methodology, the TREC was designed and evaluated by circuit simulation. The proper operations necessary for realizing or changing any symmetric function were confirmed.