Floating Diffusion Node Research Articles

A Highly Linear CMOS Image Sensor Design Based on an Adaptive Nonlinear Ramp Generator and Fully Differential Pipeline Sampling Quantization with a Double Auto-Zeroing Technique

For a complementary metal-oxide-semiconductor image sensor with highly linear, low noise and high frame rate, the nonlinear correction and frame rate improvement techniques are becoming very important. The in-pixel source follower transistor and the integration capacitor on the floating diffusion node cause linearity degradation. In order to address this problem, this paper proposes an adaptive nonlinear ramp generator circuit based on dummy pixels used in single-slope analog-to-digital converter topology for a complementary metal-oxide-semiconductor (CMOS) image sensor. In the proposed approach, the traditional linear ramp generator circuit is replaced with the new proposed adaptive nonlinear ramp generator circuit that can mitigate the nonlinearity of the pixel unit circuit, especially the gain nonlinearity of the source follower transistor and the integration capacitor nonlinearity of the floating diffusion node. Moreover, in order to enhance the frame rate and address the issue of high column fixed pattern noise, a new readout scheme of fully differential pipeline sampling quantization with a double auto-zeroing technique is proposed. Compared with the conventional readout structure without a fully differential pipeline sampling quantization technique and double auto-zeroing technique, the proposed readout scheme cannot only enhance the frame rate but can also improve the consistency of the offset and delay information of different column comparators and significantly reduce the column fixed pattern noise. The proposed techniques are simulated and verified with a prototype chip fabricated using typical 180 nm CMOS process technology. The obtained measurement results demonstrate that the overall nonlinearity of the CMOS image sensor is reduced from 1.03% to 0.047%, the efficiency of the comparator is improved from 85.3% to 100%, and the column fixed pattern noise is reduced from 0.43% to 0.019%.

A Fully Integrated DAC for CMOS Position-Based Charge Qubits with Single-Electron Detector Loopback Testing

This letter presents a fully integrated interface circuitry with a position-based charge qubit structure implemented in 22-nm FDSOI CMOS. The quantum structure is controlled by a tiny capacitive DAC (CDAC) that occupies $3.5\times 45\,\,\mu \text{m}^{2}$ and consumes 0.27mW running at a 2-GHz system clock. The state of the quantum structure is measured by a single-electron detector that consumes 1mW (including its output driver) with an area of $40\times 25\,\,\mu \text{m}^{2}$ . The low power and miniaturized layout of these circuits pave the way for integration in a large quantum core with thousands of qubits, which is a necessity for practical quantum computers. The CDAC output noise of 12 $\mu \text{V}$ -rms is estimated through mathematical analysis while the ≤ 0.225mV-rms input referred noise of the detector is verified by measurements at 3.4 K. The functionality of the system and performance of the CDAC are verified in a loopback mode with the detector sensing the CDAC-induced electron tunneling from the floating diffusion node into the quantum structure.

Dynamic Capacitance Variations Due to Barrier Modulation in Pinned Photodiode of CMOS Image Sensor

The pinned photodiode (PPD) capacitance is an important parameter in CMOS image sensor design since it provides useful information on the charge handling capacity of the photodiode. The model of the dynamic capacitance of the PPD includes a fixed depletion capacitance and a variable diffusion capacitance. The variable component of the photodiode capacitance is estimated by measuring the feedforward voltage at the floating diffusion node. However, the estimated feedforward voltage is highly nonlinear at its full-well condition. In this article, the transfer gate (TG) channel potential is shown to be dependent on the number of charges integrated in the PPD. The nonlinear behavior of TG channel potential influences the effective potential barrier. The nonlinearity observed in the feedforward voltage is also explained using the nonlinear behavior of TG channel potential. In the literature, the influence of the effective potential barrier on the photodiode capacitance models is not taken into account. In this article, the influence of the effective potential barrier on the full-well capacity, feedforward effect, and PPD capacitance is studied. The improved photodiode capacitance model using the effective potential barrier is in good agreement with the measurement results.

CMOS Image Sensor with Tunable Conversion Gain for Improved Performance

This paper describes the use of shallow trench isolation as a modified trench capacitor in CMOS image sensor. MTC helps to tune the conversion gain at the floating diffusion (FD) node. The use of MTC in pixel improves the sensitivity of the pixel without affecting the dynamic range (DR) of the pixel. The proposed pixel structure uses an existing in-built isolation trench as a capacitor. During low illumination, the MTC is separated from the floating diffusion (FD) node thus makes it easier to detect the low light signals owing to the lower FD node capacitance. However, in the event of high illumination, MTC is connected in parallel to the FD node increasing the capacity to store more charges from the photodiode. This attributed to the improved DR performance of the pixel. Using 2D numerical simulations, we show that an overall 60 dB enhancement in the DR as compared to the conventional pixel. Moreover, the proposed modification does not affect the other pixel characteristics such as dark current and crosstalk.

Pixel Optimizations and Digital Calibration Methods of a CMOS Image Sensor Targeting High Linearity

In this paper, different methodologies are employed to improve the linearity performance of a prototype CMOS image sensor (CIS). First, several pixel structures, including a novel pixel design based on a capacitive trans-impedance amplifier (CTIA), are proposed to achieve a higher pixel-level linearity. Furthermore, three types of digital linearity calibration methods are explored. A prototype image sensor designed in 0.18- $\mu \text{m}$ , 1-poly, and 4-metal CIS technology with a pixel array of $128 \times 160$ is used to verify these linearity improvement techniques. The measurement results show that the proposed CTIA pixel has the best linearity result out of all pixel structures. Meanwhile, the proposed calibration methods further improved the linearity of the CIS without changing the pixel structure. The pixel mode method achieves the most significant improvement on the linearity. One type of 4T pixel attains a nonlinearity of 0.028% with pixel mode calibration, which is two times better than the state of the art. Voltage mode (VM) and current mode (CM) calibration methods get rid of the limitation on the illumination condition during calibration operation; especially, CM calibration can further suppress the nonlinearity caused by the integration capacitor $C_{\textit {FD}}$ on the floating diffusion node, which is remnant in VM.

Partial reset HDR image sensor with improved fixed pattern noise performance

An efficient method is presented to achieve 4T pixel dynamic range extension whilst keeping the fixed pattern noise (FPN) low. The method utilizes the floating diffusion node as a secondary photocharge integration node with a partial reset applied to the floating diffusion node. The output image signal is a recombination of the linear signal integrated in the photodiode node, and a compressed signal integrated in the floating diffusion node. The recombination algorithm suppresses the FPN stemming from the variable transfer gate potential barrier height. An image sensor array of 1344x1008 pixels was built in 0.11um technology. We demonstrate the preservation of low light sensitivity of 4T pixels, a dark noise of 3.5e-, and a dynamic range for the current sensor of 115 dB, with potential to greatly exceed 120-dB. Further, the FPN stemming from the transfer gate potential barrier height variation does not degrade the image; the pixel compressive response can be controlled on a per frame basis depending on the scene, and the HDR scene is captured during one frame. The sensor combines the properties that are crucial for automotive and other machine vision applications.

CMOS Image Sensor with Dual-Sensitivity Photodiodes and Switching Circuit for Wide Dynamic Range Operation

Conventional CMOS image sensors (CISs) have a trade-off relationship between dynamic range and sensitivity. In addition, their sen-sitivity is determined by the photodiode capacitance. In this paper, CISs that consist of dual-sensitivity photodiodes in a unit pixel are proposed for achieving wide dynamic ranges. In the proposed CIS, signal charges are generated in the dual photodiodes during inte-gration, and these generated signal charges are accumulated in the floating-diffusion node. The signal charges generated in the high-sen-sitivity photodiodes are transferred to the input of the comparator through an additional source follower, and the signal voltages converted by the source follower are compared with a reference voltage in the comparator. The output voltage of the comparator deter-mines which photodiode is selected. Therefore, the proposed CIS composed of dual-sensitivity photodiodes extends the dynamic range according to the intensity of light. A 94 × 150 pixel array image sensor was designed using a conventional 0.18 μm CMOS process and its performance was simulated.

A Charge Transfer Model for CMOS Image Sensors

Based on the thermionic emission theory, a charge transfer model has been developed which describes the charge transfer process between a pinned photodiode and floating diffusion (FD) node for CMOS image sensors. To simulate the model, an iterative method is used. The model shows that the charge transfer time, barrier height, and reset voltage of the FD node affect the charge transfer process. The corresponding measurement results obtained from two different test chips are presented in this paper. The model also predicts that other physical parameters, such as the capacitance of the FD node and the area of the photodiode, will affect the charge transfer. Furthermore, the model can be extended to explain the pinning voltage measurement method and the feedforward effect.

A 0.27e-rms Read Noise 220-μV/e-Conversion Gain Reset-Gate-Less CMOS Image Sensor With 0.11-μm CIS Process

A low temporal read noise and high conversion gain reset-gate-less CMOS image sensor (CIS) has been developed and demonstrated for the first time at photoelectron-counting-level imaging. To achieve a high pixel conversion gain without fine or special processes, the proposed pixel has two unique structures: 1) coupling capacitance between the transfer gate and floating diffusion (FD) and 2) coupling capacitance between the reset gate and FD, for removing parasitic capacitances around the FD node. As a result, a CIS with the proposed pixels is able to achieve a high pixel conversion gain of $220~\mu \text{V}/\text{e}^{ {{-}}}$ and a low read noise of 0.27e $^{-}_{\text {rms}}$ using correlated multiple-sampling-based readout circuitry.

Process techniques of charge transfer time reduction for high speed CMOS image sensors

This paper proposes pixel process techniques to reduce the charge transfer time in high speed CMOS image sensors. These techniques increase the lateral conductivity of the photo-generated carriers in a pinned photodiode (PPD) and the voltage difference between the PPD and the floating diffusion (FD) node by controlling and optimizing the N doping concentration in the PPD and the threshold voltage of the reset transistor, respectively. The techniques shorten the charge transfer time from the PPD diode to the FD node effectively. The proposed process techniques do not need extra masks and do not cause harm to the fill factor. A sub array of 32 × 64 pixels was designed and implemented in the 0.18 μm CIS process with five implantation conditions splitting the N region in the PPD. The simulation and measured results demonstrate that the charge transfer time can be decreased by using the proposed techniques. Comparing the charge transfer time of the pixel with the different implantation conditions of the N region, the charge transfer time of 0.32 μs is achieved and 31% of image lag was reduced by using the proposed process techniques.

A Low Noise Pixel Architecture for Scientific CMOS Monolithic Active Pixel Sensors

This paper presents the design and characterisation of FORTIS (4T Test Image Sensor), which is a low noise, CMOS monolithic active pixel sensor for scientific applications. The pixels present in FORTIS are based around the four transistor (4T) pixel architecture, which is already widely used in the commercial imaging community. The sensor design contains thirteen different variants of the 4T pixel architecture to investigate the effects of changing its core parameters. The variants include differences in the pixel pitch, the diode size, the in-pixel source follower, and the capacitance of the floating diffusion node (the input node of the in-pixel source follower). Processing variations have also been studied, which include varying the resistivity of the epitaxial layer and investigating the effects of a special deep p-well layer. By varying these parameters, the 4T pixel architecture can be optimised for scientific applications where detection of small amounts of charge is required.

A Dual-Capture Wide Dynamic Range CMOS Image Sensor Using Floating-Diffusion Capacitor

A dual-capture wide dynamic range CMOS image sensor using an in-pixel floating-diffusion (FD) storage capacitor is proposed. The proposed structure uses the FD as a storage capacitor. The potential of the FD node is read out using a floating-gate capacitor without a contact metallization of the FD node to reduce the leakage. The proposed sensor was fabricated using a 0.35-mum CMOS process. The chip includes 320 times 240 pixels whose pitch is 5.6 mum and whose fill factor is 36%. The measurement results show 100-dB dynamic range, and the leakage at the non-metalized FD is reduced to about one-third of that of the conventional FD with the contact metallization.

A Spatial-Temporal Multiresolution CMOS Image Sensor With Adaptive Frame Rates for Tracking the Moving Objects in Region-of-Interest and Suppressing Motion Blur

In this paper, we report a CMOS image sensor for spatial-temporal multiresolution images. This image sensor simultaneously generates two outputs: one for normal images (<30 fps) of stationery background and the other for adaptable frame-rate images (over 960 fps) of moving objects. The moving objects are tracked with a reduced spatial resolution in the region-of-interest (ROI). The entire image is reconstructed from the two images with the details in stationery objects and the suppressed motion blur in moving objects. High frame rate only applies to the ROI; therefore, the proposed scheme can significantly reduce power consumption by adjusting the optimal use of bandwidth. In order to provide real-time decision of ROI, the sensor employs on-chip motion-detection circuits based on the inter-pixel switch operation by storing the previous frame signal in a floating diffusion node. This allows a small pixel implementation without adding any extra in-pixel memory components. A prototype chip has been implemented using a 0.35 mum 1P4M standard CMOS process and multiresolution images have been successfully captured. The fabricated chip operates at 3.3 V and consumes 75 mW in the multiresolution readout of a 256times256 normal image at 30 fps and a 64times64 ROI image at 240 fps.

Operation Principles of 0.18-$muhboxm$Four-Transistor CMOS Image Pixels With a Nonfully Depleted Pinned Photodiode

The operation principles of the four-transistor (4-TR) pixel CMOS image sensor, fabricated by 0.18-mum technology, were investigated by pixel-level characterization utilizing a single-pixel test pattern. It was found that the pixel's dark current level is strongly influenced by the gate bias (VTX(on)) of the transfer (TX) transistor at a fixed supply voltage (VDD). The largest dark current occurred at a conventional bias condition of VTX(on)=VDD=2.5V, but the dark current level was reduced by less than one-third at VTX(on)=2.1V without degrading the pixel's charge transfer capabilities. Attributed to the dark current reduction, the fixed-pattern noise (FPN) of pixel was also decreased by up to 13.3 dB. These improvements can be explained by the more effective reset of pinned photodiode (PPD) at VTX(on)=2.1V, especially in the pixel with VDD of 2.5 V or lower in which the full of PPD becomes more and more difficult. In this bias condition, namely nonfully PPD condition, the TX transistor was proven to operate in the deepest depletion mode by effectively suppressing the electron injection from floating diffusion node to channel. Moreover, various driving signals to the TX transistor were applied to do more detailed physical analysis of the pixel operation. Since the dark current and FPN are main bottlenecks in most CMOS image sensors, the proposed method is expected to efficiently improve the performance of 4-TR CMOS image pixels under 2.5 V or lower operational voltages

The effects of deuterium annealing on the reduction of dark currents in the CMOS APS

The effects of low-temperature deuterium annealing on the reduction of dark currents in the CMOS active pixel sensor (APS) have been investigated. Experimental results reveal that deuterium annealing is more effective in reducing dark currents of the CMOS APS than conventional forming gas annealing, because it shows the enhanced passivation efficiency of the interface traps located in the sidewall of the shallow trench isolation. From the characterization results of test structures, it is found that the dark currents generated from the photodiode and floating diffusion node region can be reduced more effectively by using the deuterium annealing process.

The Analysis of Dark Signals in the CMOS APS Imagers From the Characterization of Test Structures

The characteristics of dark signals have been investigated in the CMOS active pixel sensor (APS) with test structures fabricated using the deep-submicron CMOS technology. It is found that the periphery of the photodiode (PD) is the dominant source of dark currents in our test structure, and this factor is very sensitive to the distance between the sidewall of the shallow trench isolation and the n-type region of the PD. The dark currents from the transfer gate can be effectively reduced by the tail of p/sup +/ region on the surface of the transfer gate, and those from the floating diffusion (FD) node were estimated to be negligible in the normal operational mode. However, because of the enhanced thermal generation velocity caused by the severe process-induced damages, the FD node was considered as the main source of increased dark currents in the single frame capture mode. The characteristics of quantized dark currents causing the white pixels in the CMOS APS were examined using the dark current spectroscopy method. Three distinct deep-level bulk traps have been identified with the location in the silicon bandgap at |E/sub t/-E/sub i/|/spl sim/0.020 (eV), |E/sub t/-E/sub i/|/spl sim/0.082 (eV), and |E/sub t/-E/sub i/|/spl sim/0.058 (eV), and capture cross sections of 7.80/spl times/10/sup -15/ cm/sup 2/, 1.83/spl times/10/sup -13/ cm/sup 2/, and 1.46/spl times/10/sup -13/ cm/sup 2/ respectively.

論文小特集 リニアセンサ技術 １００ＭＨｚ５ｋビットリニアイメージセンサ

This paper describes a 100-MHz datarate, 5000 element CCD linear image sensor with 20.3μ V/electron amplifier sensitivity. A reset-pulse level-adjustment circuit with a reset gate potential detector, and a self-aligned technique to minimize floating diffusion node capacitance are used to achieve this performance. The reading speed is triple and the photo-sensitivity is twice that of conventional linear image sensors with more than 5000 elements.This sensor is able to scan an 11-inch sheet in 50 μs with 400-dot-per-inch resolution.

A controllable piecewise linear-output circuit for CCD multiplexers

In certain applications, the single gain of the familiar reset-gate floating-diffusion output circuit limits the performance of a charge-coupled device (CCD) multiplexer used in a focal-plane array (FPA). Incorporation of an additional capacitor at the floating-diffusion node along with a switching MOSFET allows the output circuit to controllably switch from a high-gain to a low-gain state, thereby increasing the performance when detecting both large and small charge packets. This paper first describes such a circuit and then presents experimental results to verify its theory of operation. Discussion of a particular application is also given.