Flipped Bits Research Articles

ALERT: A lightweight defense mechanism for enhancing DNN robustness against T-BFA

DNNs have become pervasive in many security–critical scenarios such as autonomous vehicles and medical diagnoses. Recent studies reveal the susceptibility of DNNs to various adversarial attacks, among which weight Bit-Flip Attacks (BFA) is emerging as a significant security concern. Moreover, Targeted Bit-Flip Attacks (T-BFA), as a novel variant of BFA, can stealthily alter specific source–target classifications while preserving accurate classifications of non-target classes, posing a more severe threat. However, due to the inadequate consideration for T-BFA’s “targeted” characteristic, existing defense mechanisms tend to perform over-protection/-modification to the network, leading to significant defense overheads or non-negligible DNN accuracy reduction.In this work, we propose ALERT, ALightweight defense mechanism for Enhancing DNN Robustness against T-BFA while maintaining network accuracy. Firstly, fully understanding the key factors that dominate the misclassification among source–target class pairs, we propose a Source-Target-Aware Searching (STAS) method to accurately identify the vulnerable weights under T-BFA. Secondly, leveraging the intrinsic redundancy characteristic of DNNs, we propose a weight random switch mechanism to reduce the exposure of vulnerable weights, thereby weakening the expected impact of T-BFA. Striking a delicate balance between enhancing robustness and preserving network accuracy, we develop a metric to meticulously select candidate weights. Finally, to further enhance the DNN robustness, we present a lightweight runtime monitoring mechanism for detecting T-BFA through weight signature verification, and dynamically optimize the weight random switch strategy accordingly. Evaluation results demonstrate that our proposed method effectively enhances the robustness of DNNs against T-BFA while maintaining network accuracy. Compared with the baseline, our method can tolerate 6.7× more flipped bits with negligible accuracy loss (<0.1% in ResNet-50).

Impeccable Keccak

The standardization of the hash-based digital signature scheme SPHINCS+ proceeds faster than initially expected. This development seems to be welcomed by practitioners who appreciate the high confidence in SPHINCS+’s security assumptions and its reliance on well-known hash functions. However, the implementation security of SPHINCS+ leaves many questions unanswered, due to its proneness to fault injection attacks. Previous works have shown, that even imprecise fault injections on the signature generation are sufficient for universal forgery. This led the SPHINCS+ team to promote the usage of hardware countermeasures against such attacks. Since the majority of operations in SPHINCS+ is dedicated to the computation of the Keccak function, we focus on its security. At the core, hardware countermeasures against fault injection attacks are almost exclusively based on redundancy. For hash functions such as Keccak, straightforward instance- or time-redundancy is expensive in terms of chip area or latency. Further, for applications that must withstand powerful fault adversaries, these simple forms of redundancy are not sufficient. To this end, we propose our impeccable Keccak design. It is based on the methodology presented in the original Impeccable Circuits paper by Aghaie et al. from 2018. On the way, we show potential pitfalls when designing impeccable circuits and how the concept of active security can be applied to impeccable circuits. To the best of our knowledge, we are the first to provide proofs of active security for impeccable circuits. Further, we show a novel way to implement non-linear functions without look-up tables. We use our findings to design an impeccable Keccak. Assuming an adversary with the ability to flip single bits, our design detects all attacks with three and less flipped bits. Attacks from adversaries who are able to flip four or more bits are still detected with a high probability. Thus, our design is one of the most resilient designs published so far and the only Keccak design that is provably secure within a bit-flip model. At an area overhead of factor 3.2, our design is competitive with state-of-the-art designs with less resilience.

Two-Round Selection-Based Bit Flipping Decoding Algorithm for LDPC Codes

This paper presents a novel iterative reliability-based bit flipping (BF) algorithm for decoding low-density parity-check codes. The new decoder is a single BF algorithm called two-round selection -based bit flipping. It introduces the idea of a two-round selection of the flipped bit, based successively on hard and soft received channel values. In the first stage, a set of unreliable bits is identified, and then a second selection is used, to pick out among them the bit to flip. In the second round of selection, the initial belief about received signals, contributes efficiently to selecting the best candidate bit. We demonstrate through simulations over the binary-input additive white Gaussian noise channel and the Rayleigh fading channel that the proposed algorithm exhibits better decoding performance when compared with some well-known soft decision BF algorithms. A complexity analysis of the proposal and a comparison to other BF decoders are also presented.

Versatile Weight Attack via Flipping Limited Bits.

Many attack paradigms against deep neural networks have been well studied, such as the backdoor attack in the training stage and the adversarial attack in the inference stage. In this article, we study a novel attack paradigm, the bit-flip based weight attack, which directly modifies weight bits of the attacked model in the deployment stage. To meet various attack scenarios, we propose a general formulation including terms to achieve effectiveness and stealthiness goals and a constraint on the number of bit-flips. Furthermore, benefitting from this extensible and flexible formulation, we present two cases with different malicious purposes, i.e., single sample attack (SSA) and triggered samples attack (TSA). SSA which aims at misclassifying a specific sample into a target class is a binary optimization with determining the state of the binary bits (0 or 1); TSA which is to misclassify the samples embedded with a specific trigger is a mixed integer programming (MIP) with flipped bits and a learnable trigger. Utilizing the latest technique in integer programming, we equivalently reformulate them as continuous optimization problems, whose approximate solutions can be effectively and efficiently obtained by the alternating direction method of multipliers (ADMM) method. Extensive experiments demonstrate the superiority of our methods.

Predicting positions of flipped bits in robust image hashes

Both robust and cryptographic hash methods have advantages and disadvantages. It would be ideal if robustness and cryptographic confidentiality could be combined. The problem here is that the concept of similarity of robust hashes cannot be applied to cryptographic hashes. Therefore, methods must be developed to reliably intercept the degrees of freedom of robust hashes before they are included in a cryptographic hash, but without losing their robustness. To achieve this, we need to predict the bits of a hash that are most likely to be modified, for example after a JPEG compression. We show that machine learning can be used to make a much more reliable prediction than the approaches previously discussed in the literature.

Emulator of Gene Mutation: Interfering True Random Number Generators Using Resistive-Gate Non-Volatile-Memories

We present the interfering True-random-number-generators (TRNG) composed of 2 parallel resistive-gate non-volatile memory cells. Both cells store closer but different resistance states. 2 cells output current flows separately, which are received concurrently by a current-reference sense amplifier (SA). The SA compares difference of received flows and then continues outputting the same bits if difference of current-flows remains stable. However, if randomness happens, levels of current flows from the cells are interlaced; the SA will output a flipped bit, which can be in analogy to gene mutation. So, we emulate mutation by the interfering TRNGs and propose an algorithm to implement emulator of mutation. The TRNGs are also qualified by cryptographic tests, including the Hamming distance, Hamming weight, auto-correlation, and tests of National Institute of Standards and Technologies.

PAPR reduction methods based on bit flipping

ABSTRACT In this work, two peak-to-average-power ratio (PAPR) reduction methods based on bit flipping are designed for OFDM signals. Rather than sending side information, error correction codes are used to recover the flipped bits, as well as to protect the transmitted data. The first PAPR reduction method combines hard-decision decoding (HDD) and natural mapping. Taking advantage of the fact that the natural mapping symbol is represented as a linear combination of the included bits, the flipping bits can be selected at low complexity. The concept of compressed sensing is introduced in order to minimize the number of flipping bits and retain most of the code distance for error correction. In the second method, a low-density parity-check (LDPC) code is cascaded as an inner code following the HDD code, and Gray mapping is used. Soft-decision decoding (SDD) is applied to the LDPC code, which significantly improves the data protection capability, then the outer HDD code is able to focus on recovering the flipped bits. The designs proposed in this paper show great flexibility and provide a trade-off between PAPR reduction and the error-correction capability.

A Low-Complexity Endurance Modulation for Flash Memory

The repeated program/erase (P/E) cycles wear out flash memory cells which limits the device’s lifetime. The larger the injected/erased charge, the faster the wear out rate and thus there is interest in reducing the percentage of cells programmed to high voltage levels. Conventional data shaping techniques often introduce a nonnegligible overhead as well as incurring additional complexity to encode the input data into shaped codewords and decode the read data. We propose a novel lossless yet simple endurance modulation technique that relies solely on the error-correction code (ECC) to retrieve the original data. This idea is motivated by the fact that ECCs are usually designed to correct channel errors towards the end of the device’s lifetime and hence at early age, the ECC can be jointly used for channel error correction and endurance demodulation. The proposed scheme consists of data shaping by flipping bits in a controlled manner and simple max-log demodulation to recover those flipped bits. The simulation results show that the proposed scheme does not undermine the device’s ability to recover the original data if the shaping gain is adjusted as the device ages. Once the channel errors exceed a prescribed threshold, the controller disables the endurance modulation and operates in normal mode.

SpotSDC: Revealing the Silent Data Corruption Propagation in High-Performance Computing Systems.

The trend of rapid technology scaling is expected to make the hardware of high-performance computing (HPC) systems more susceptible to computational errors due to random bit flips. Some bit flips may cause a program to crash or have a minimal effect on the output, but others may lead to silent data corruption (SDC), i.e., undetected yet significant output errors. Classical fault injection analysis methods employ uniform sampling of random bit flips during program execution to derive a statistical resiliency profile. However, summarizing such fault injection result with sufficient detail is difficult, and understanding the behavior of the fault-corrupted program is still a challenge. In this article, we introduce SpotSDC, a visualization system to facilitate the analysis of a program's resilience to SDC. SpotSDC provides multiple perspectives at various levels of detail of the impact on the output relative to where in the source code the flipped bit occurs, which bit is flipped, and when during the execution it happens. SpotSDC also enables users to study the code protection and provide new insights to understand the behavior of a fault-injected program. Based on lessons learned, we demonstrate how what we found can improve the fault injection campaign method.

Sparse Robust Learning From Flipped Bits

In wireless sensor networks (WSNs), distributed sensors are often constrained by their limited battery energy and radio spectrum for transmission. This paper investigates an on-line parameter estimation problem of linear regression in a WSN, where each sensor is restricted to send a one-bit message $+1/-1$ to a fusion center in order to satisfy the spectrum and power constraints. Moreover, sensor nodes communicate with the fusion center over noisy links, which can randomly flip the binary message sent from each sensor to the fusion center. With the flipped bit stream, robust and sparse-robust learning algorithms respectively are proposed. In the proposed algorithms, the parameter estimation over a WSN with the imperfect binary communication is formulated hierarchically as Bayesian learning, and is equivalent to an expectation maximization realized by using the recursive least-squares methods. Theoretical and empirical research is carried out to assess the performance of the proposed algorithms, and a practical application of the proposed algorithms in estimation and tracking of frequencies of multiple sinusoids is also presented. These theoretical analysis and experimental results demonstrate the effectiveness of the proposed algorithms.

Performance Monitoring for Live Systems with Soft FEC and Multilevel Modulation

Performance monitoring is an essential function for margin measurements in live systems. Historically, system budgets have been described by the Q-factor converted from the bit error rate (BER) under binary modulation and direct detection. The introduction of hard-decision forward error correction (FEC) did not change this. In recent years technologies have changed significantly to comprise coherent detection, multilevel modulation and soft FEC. In such advanced systems, different metrics such as (nomalized) generalized mutual information (GMI/NGMI) and asymmetric information (ASI) are regarded as being more reliable. On the other hand, Q budgets are still useful because pre-FEC BER monitoring is established in industry for live system monitoring. The pre-FEC BER is easily estimated from available information of the number of flipped bits in the FEC decoding, which does not require knowledge of the transmitted bits that are unknown in live systems. Therefore, the use of metrics like GMI/NGMI/ASI for performance monitoring has not been possible in live systems. However, in this work we propose a blind soft-performance estimation method. Based on a histogram of log-likelihood-values without the knowledge of the transmitted bits, we show how the ASI can be estimated. We examined the proposed method experimentally for 16 and 64-ary quadrature amplitude modulation (QAM) and probabilistically shaped 16, 64, and 256-QAM in recirculating loop experiments. We see a relative error of 3.6%, which corresponds to around 0.5 dB signal-to-noise ratio difference for binary modulation, in the regime where the ASI is larger than the assumed FEC threshold. For this proposed method, the digital signal processing circuitry requires only a minimal additional function of storing the L-value histograms before the soft-decision FEC decoder.

A Deliberate Bit Flipping Coding Scheme for Data-Dependent Two-Dimensional Channels

In this paper, we present a deliberate bit flipping (DBF) coding scheme for binary two-dimensional (2-D) channels, where specific patterns in channel inputs are the significant cause of errors. The idea is to eliminate a constrained encoder and, instead, embed a constraint into an error correction codeword that is arranged into a 2-D array by deliberately flipping the bits that violate the constraint. The DBF method relies on the error correction capability of the code being used so that it should be able to correct both deliberate errors and channel errors. Therefore, it is crucial to flip minimum number of bits in order not to overburden the error correction decoder. We devise a constrained combinatorial formulation for minimizing the number of flipped bits for a given set of harmful patterns. The generalized belief propagation algorithm is used to find an approximate solution for the problem. We evaluate the performance gain of our proposed approach on a data-dependent 2-D channel, where 2-D isolated-bits patterns are the harmful patterns for the channel. Furthermore, the performance of the DBF method is compared with classical 2-D constrained coding schemes for the 2-D no isolated-bits constraint on a memoryless binary symmetric channel.

Opcode vector: An efficient scheme to detect soft errors in instructions

Bit flips on instructions may affect the execution of the processor depending on the Instruction Set Architecture (ISA) and the location of the flipped bits. Intrinsically, ISAs may detect bit upsets if the errors on the instructions produce exceptions that halt the execution. In this paper, we explore a dynamic checking of the instructions to detect errors before execution. The scheme is based on loading an approximate representation of the instructions based on a vector that identifies the opcodes used in the program in a special purpose register. During execution, instructions are first checked on the register and on a negative an error is detected as the instruction has an opcode that does not correspond to any of the ones used in the program. Since we use an approximate representation, a small number of false positives can occur for erroneous instructions which may still be detected if they lead to a system crash. The proposed opcode vector scheme is compared with the use of a Bloom filter (BF) that has been previously proposed to detect errors on instructions. In both cases, a check can produce false positives but not false negatives. The Bloom filter is built using all the bits in the instruction. On the other hand, the opcode vector uses only a few bits of the instruction. In both cases, the check is combined with a previous error propagation scheme. In the opcode case, this ensures that all errors corrupt the opcode bits while for the BF, the error propagation reduces the number of false positives. The proposed approach has two main benefits. The first one is an increase in the error detection rate as the set of valid instructions is restricted to those used in the program allowing the detection of invalid instructions even if they do not lead to a system crash. The second one is that errors are detected before the crash. This is done at the cost of adding a small register for the vector of opcodes and some control logic. This is significantly simpler than in the case of the BF that needs to compute several hash functions and access several bits on the register to perform the check. We evaluated this approach on binary files of the ARM Cortex M0 core. According to our findings, the proposed vector of opcodes is more effective to detect errors than the BF and its detection rate is less dependent on the program size. Based on those results, it seems that the proposed method can be an interesting option to detect errors in instructions for systems on which a small overhead can be introduced if it improves reliability.

Modified Gradient Descent Bit-Flipping Decoding for Low-Density Parity-Check Codes

In this paper, we modify the gradient descent bit-flipping (GDBF) decoding of low-density parity-check codes based on the syndrome. Firstly, the syndrome weight is utilized to detect the decoding loop, which seriously effects the performance of GDBF decoding. Then the syndrome information is introduced to update the reliability of the flipped bit nodes. Since the modified GDBF, denoted as MGDBF, only uses the syndrome weight and syndrome information, there is small complexity increased. Simulation results indicate that the two modifications bring about significant improvement in error-rate performance. For single MGDBF decoding, its performance is not only better than that of GDBF, but also is better than that of noisy GDBF. For multi MGDBF decoding, it can obtain fast convergence rate and good performance by employing the appropriate adaptive threshold scheme.

Dynamic Weighted Bit-Flipping Decoding Algorithms for LDPC Codes

Bit-flipping (BF) decoding of low-density parity-check codes is of low complexity but gives inferior performance in general. To improve performance and provide new BF decoder options for complexity-performance tradeoffs, we propose new designs for the flipping function (FF), the flipped bit selection (FBS) rule and the checksum weight updating schedule. The new FF adjusts the checksum weights in every iteration while our FBS rules take more information into account. These two modifications represent efforts to track more closely the evolutions of both check and variable nodes' reliabilities. Two selective update schedules are proposed to offer more performance and complexity tradeoffs. The combinations of the new FBS rule and known FFs result in new BF decoders with improved performance and a modest complexity increase. On the other hand, combining the new FF and FBS rule gives a new decoder with performance comparable to that of the normalized min-sum algorithm while if we use a much simpler FBS rule instead, the decoder suffers little performance loss with reduced complexity. We also present a simple decision-theoretical argument to justify the new checksum weight formula and a time-expanded factor graph model to explain the proposed selective weight-updating schedules.

A Dominating Error Region Strategy for Improving the Bit-Flipping LDPC Decoder of SSDs

This brief presents a dominating error region strategy (DERS) that improves the bit-flipping (BF) low-density parity-check decoder for solid-state drives. With the help of the DERS, the state-of-the-art BF decoding algorithms achieve better error correction performance while taking less iterations. Specifically, the DERS provides solutions for restricting the occurrences of an even number of flipped bits and bit-error propagations, both of which are intrinsic problems to current BF decoding algorithms. The DERS can be implemented with a simple circuitry and serve as a fine-tuning technique for the decoding reliability–performance tradeoff. In this brief, the DERS is evaluated with numerical analysis and computer simulations.

Fast weighted bit flipping algorithm for higher-speed decoding of Low-Density Parity-Check codes

Because of the speed limitation of the conventional bit-selection strategy in the existing weighted bit flipping algorithms, a high-speed Low-Density Parity-Check (LDPC) decoder cannot be realised. To solve this problem, we propose a fast weighted bit flipping algorithm. Specifically, based on the identically distributed error bits, a parallel bit-selection method is proposed to reduce the selection delay of the flipped bits. The delay analysis demonstrates that, the decoding speed of LDPC codes can be significantly improved by the proposed algorithm. Furthermore, simulation results verify the validity of the proposed algorithm.

An RLL-Constrained LDPC Coded Recording System Using Deliberate Flipping and Flipped-Bit Detection

In this paper, a low-density parity-check (LDPC) coded recording system is investigated, for which the run-length-limited (RLL) constraint is satisfied by deliberate flipping at the write side and by estimating the flipped bits at the read side. Two approaches are proposed for enhancing the error performance of such a system. The first approach is to alleviate the negative effect of incorrect estimation of the flipped bits by adjusting the soft information. The second approach is to increase the likelihood of the correct detection of flipped bits by designing a flipped-bit detection algorithm that utilizes both the RLL constraint and the parity-check constraint of the LDPC code. These two approaches can be combined to obtain significant improvement in performance over previously proposed methods.

Reconstructing a Linear Scrambler With Improved Detection Capability and in the Presence of Noise

In this paper, the problem of reconstruction of the feedback polynomial in a linear scrambler is studied. Our work contains two parts. In the first part, schemes to improve the performance of an existing reconstruction algorithm are proposed. Simulation results show that both the detection capability and speed of the existing algorithm are significantly improved by using our proposed schemes. In the second part, the reconstruction of linear scramblers in the presence of channel noise is investigated. We consider flipped bits due to noise as well as insertion of bits in the scrambled bit sequence. For both cases, factors which affect the performance of the reconstruction algorithm are discussed.

Measuring Diffusion in Stream Ciphers using Statistical Testing Methods

Confusion and diffusion suggested by Claude Shannon are two techniques that symmetric key ciphers should satisfy to prevent cryptanalysis. Diffusion dissipates the statistical properties of the plaintext over the whole ciphertext. For a block cipher, each bit of the output ciphertext block changes with probability one half for any flipped bit in the input plaintext block, implying the cipher to have good diffusion properties. This definition with slight modification can also be applied to stream ciphers but here it is enough to make sure the following: (i) to ensure an overall change in the output keystream with probability half for any flipped bit in the Key-IV bit sequence, and (ii) to verify that every bit in the output keystream changes with probability one half for any single bit flip in the key-IV bit sequence. Here we insist on using these tests together for measuring diffusion in stream ciphers. Based on this we have examined the level of diffusion exhibited by some of the eSTREAM candidates and the result is given in this paper. Defence Science Journal, 2012, 62(1), pp.6 -10 , DOI:http://dx.doi.org/10.14429/dsj. 62.1435