Flexible Field Programmable Gate Array Research Articles

The upgrade of the CMS electromagnetic calorimeter for HL-LHC

The High Luminosity upgrade of the Large Hadron Collider (HL-LHC) at CERN aims to achieve unprecedented levels of instantaneous and integrated luminosities, approximately 5 × 1034 cm-2 s-1 and 3000 fb-1, respectively. It is anticipated that each bunch-crossing will result in an average of 140 to 200 collisions (pileup). The lead tungstate crystals and avalanche photodiodes (APDs) in the barrel region of the electromagnetic calorimeter (ECAL) of the Compact Muon Solenoid (CMS) will remain effective. However the readout and trigger electronics will undergo complete replacement to keep the current level of performance. A dual gain trans-impedance amplifier and an application-specific integrated circuit will be installed, providing two 160 MS/s analog-to-digital converter channels, gain selection, and data compression. The increase in noise within the APDs, due to radiation-induced dark current, will be alleviated by reducing the operating temperature of the ECAL. Additionally, the trigger primitive formation will be shifted away from the detector and handled by powerful and flexible field-programmable gate array processors housed on the back-end electronics cards.In this document, the complete ECAL barrel readout chain design and the current state of research and development for each individual component regarding the upgrade will be described. The outcomes of recent test beam campaigns conducted at the CERN SPS, exploiting electron beams with energies of up to 250 GeV, will also be summarized. Notably, measurements pertaining to the energy resolution performance of the latest prototypes of HL-LHC ECAL readout electronics will be presented.

An integrated and scalable experimental system for nitrogen-vacancy ensemble magnetometry.

Nitrogen-vacancy (NV) centers in diamond are extremely promising solid-state spin quantum sensors for magnetic field in recent years. The rapid development of NV-ensemble magnetometry has put forward higher requirements for high-speed data acquisition, real-time signal processing and analyzing, etc. However, the existing commercial instruments are bulky and expensive, which brings extra complexity to the weak magnetic field detection experiment and hinders the practicality and miniaturization of NV-ensemble magnetometry. Here, we report on an integrated and scalable experimental system based on a field-programmable-gate-array (FPGA) chip assisted with high-speed peripherals for NV-ensemble magnetometry, which presents a compact and compatible design containing high-speed data acquisition, oscilloscopes, signal generator, spectrum analyzer, lock-in amplifier, proportional-integral-derivative feedback controller, etc. To verify its applicability and reliability in experiments, various applications, such as optical magnetic resonance detection, optical cavity locking, and lock-in NV magnetometry, are conducted. We further realize the pump-enhanced magnetometry based on NV center ensembles using the optical cavity. Through the flexible FPGA design approach, this self-developed device can also be conveniently extended into atomic magnetometer and other quantum systems.

CMS ECAL upgrade for precision timing and energy measurements at the High Luminosity LHC

The unprecedented instantaneous luminosity provided by the High Luminosity upgrade of the LHC (HL-LHC) at CERN requires an upgrade of the Compact Muon Solenoid (CMS) electromagnetic calorimeter (ECAL). The barrel region of the CMS ECAL will be preserved but will be operated at a lower temperature and with a completely new readout and trigger electronics. A dual gain trans-impedance amplifier and an integrated circuit providing two 160 MHz analog to digital converter channels, gain selection, and data compression will be used in the new readout electronics. The trigger decision will be moved off-detector and performed by powerful and flexible field programmable gate array processors, allowing for sophisticated trigger algorithms to be applied. The upgraded ECAL will be capable of high-precision energy measurements throughout HL-LHC data taking and will greatly improve the time resolution for photons and electrons above 10 GeV.

Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA

The quasi-cyclic (QC) low-density parity-check (LDPC) code is a key error correction code for the fifth generation (5G) of cellular network technology. Designed to support several frame sizes and code rates, the 5G LDPC code structure allows high parallelism to deliver the high demanding data rate of 10 Gb/s. This impressive performance introduces challenging constraints on the hardware design. Particularly, allowing such high flexibility can introduce processing rate penalties on some configurations. In this context, a novel highly parallel and flexible hardware architecture for the 5G LDPC decoder is proposed, targeting field-programmable gate array (FPGA) devices. The architecture supports frame parallelism to maximize the utilization of the processing units, significantly improving the processing rate. The controller unit was carefully designed to support all 5G configurations and to avoid update conflicts. Furthermore, an efficient data scheduling is proposed to increase the processing rate. Compared to the recent related state of the art, the proposed FPGA prototype achieves a higher processing rate per hardware resource for most configurations.

The VMM readout system

The New Small Wheel Upgrade of the ATLAS experiment at CERN, planned to take place at 2020, requires a new generation of front-end electronics that will support its data acquisition requirements. The VMM Application-Specific Integrated Circuit has been in development for the last seven years to serve as the foundation of the New Small Wheel’s readout scheme. It has gone through three major revisions and a minor one, the latter being the production version. To facilitate the testing and readout of the VMM, as well as to study its detector performance, a complete readout system has been developed. It consists of flexible Field-Programmable Gate Array logic with extensive functionality, and an efficient software framework providing the user interface. This system, referred to as the ”The VMM Readout System”, has been used in test-beam campaigns at CERN, as well as in bench calibration and testing measurement scenarios for the past several years, supporting all readout modes and features of the VMM.

Compact and Flexible FPGA Implementation of Ed25519 and X25519

This article describes a field-programmable gate array (FPGA) cryptographic architecture, which combines the elliptic curve--based Ed25519 digital signature algorithm and the X25519 key establishment scheme in a single module. Cryptographically, these are high-security elliptic curve cryptography algorithms with short key sizes and impressive execution times in software. Our goal is to provide a lightweight FPGA module that enables them on resource-constrained devices, specifically for Internet of Things (IoT) applications. In addition, we aim at extensibility with customisable countermeasures against timing and differential power analysis side-channel attacks and fault-injection attacks. For the former, we offer a choice between time-optimised versus constant-time execution, with or without Z -coordinate randomisation and base-point blinding; and for the latter, we offer enabling or disabling default-case statements in the Finite State Machine (FSM) descriptions. To obtain compactness and at the same time fast execution times, we make maximum use of the Digital Signal Processing (DSP) slices on the FPGA. We designed a single arithmetic unit that is flexible to support operations with two moduli and non-modulus arithmetic. In addition, our design benefits in-place memory management and the local storage of inputs into DSP slices’ pipeline registers and takes advantage of distributed memory. These eliminate a memory access bottleneck. The flexibility is offered by a micro-code supported instruction-set architecture. Our design targets 7-Series Xilinx FPGAs and is prototyped on a Zynq System-on-Chip (SoC). The base design combining Ed25519 and X25519 in a single module, and its implementation requires only around 11.1K Lookup Tables (LUTs), 2.6K registers, and 16 DSP slices. Also, it achieves performance of 1.6ms for a signature generation and 3.6ms for a signature verification for a 1024-bit message with an 82MHz clock. Moreover, the design can be optimised only for X25519, which gives the most compact FPGA implementation compared to previously published X25519 implementations.

Burst-Mode FPGA Implementation and Error Location Analysis of Forward Error Correction for Passive Optical Networks

Forward error correction (FEC) based on Reed–Solomon coding for the burst-mode upstream traffic of passive optical networks (PONs) is analyzed in detail using flexible field-programmable gate arrays (FPGAs). In order to achieve true burst-mode transmission using FPGAs, specific architectural solutions are required. In particular, a burst-mode frame synchronizer and a burstmode Reed–Solomon decoder are described in detail and analyzed experimentally within a state-of-the-art longreach PON test-bed. During this analysis, the upstream FEC performance is impaired by introducing strongly correlated and localized errors within the burst through the reduction of the burst preamble duration. The observed FEC degradation is exhaustively analyzed by implementing on the FPGAs a tool for error location analysis and frame loss measurements. This investigation demonstrates the importance of understanding the error distribution within the burst in order to correctly estimate the FEC performance in PON upstream links.

A flexible FPGA based QDC and TDC for the HADES and the CBM calorimeters

A Charge-to-Digital-Converter (QDC) and Time-to-Digital-Converter (TDC) based on a commercial FPGA (Field Programmable Gate Array) was developed to read out PMT signals of the planned HADES electromagnetic calorimeter (ECAL) at GSI Helmholtzzentrum für Schwerionenforschung GmbH (Darmstadt, Germany). The main idea is to convert the charge measurement of a detector signal into a time measurement, where the charge is encoded in the width of a digital pulse, while the arrival time information is encoded in the leading edge time of the pulse. The PaDiWa-AMPS prototype front-end board for the TRB3 (General Purpose Trigger and Readout Board—version 3) which implements this conversion method was developed and qualified. The already well established TRB3 platform provides the needed precise time measurements and serves as a data acquisition system. We present the read-out concept and the performance of the prototype boards in laboratory and also under beam conditions. First steps have been completed in order to adapt this concept to SiPM signals of the hadron calorimeter in the CBM experiment at the planned FAIR facility (Darmstadt).

Accelerated join evaluation in Semantic Web databases by using FPGAs

SummaryWhile the amount of information steadily increases, the requirements on the response time to query these information become more strict. Under those conditions, conventional database systems reach their limits and cannot meet these performance requirements anymore. In recent years, systems with many processing cores are considered to satisfy these demands. Furthermore, these systems include more and more heterogeneous cores tailor‐made to solve one specific task in an efficient manner. However, dedicated hardware accelerators are inflexible and cannot be adapted to the requirements of a dedicated query. Thus, the challenge is orchestrating the diversity of the functionality of all the cores to be optimized for performance/energy efficiency. In this paper, a concept is introduced on how to develop a flexible Field‐Programmable Gate Arrays (FPGA)‐based hardware accelerator to improve the performance of query evaluation in a Semantic Web database. As a first step to the hardware/software system, several joint algorithms are implemented on an FPGA and evaluated against a well‐developed software solution (implemented in C). The comparison shows a significant speedup of up to 10 times. Because of the complexity of the join operator, it is promising that the overall performance of query evaluation can be further enhanced by processing whole queries on an FPGA. Copyright © 2015 John Wiley & Sons, Ltd.

Can COTS Ethernet Switches Handle Uncompressed Video?

The carriage of realtime video over Ethernet networks promises significant benefits to the broadcast industry. But there has been some concern about whether commercial-off-the-shelf Ethernet switches can meet broadcast quality of service requirements. This paper describes the results of a range of static and dynamic tests of Ethernet switches using packet flows that are representative of uncompressed high-definition video encapsulated in SMPTE 2022-6, looking specifically at packet loss, packet reordering, latency, and packet delay variation. Flow test generators and analyzers include a new flexible field-programmable gate array architecture, controlled using a RESTful application programming interface.

A versatile LabVIEW and field-programmable gate array-based scanning probe microscope for in operando electronic device characterization.

Understanding the complex properties of electronic and spintronic devices at the micro- and nano-scale is a topic of intense current interest as it becomes increasingly important for scientific progress and technological applications. In operando characterization of such devices by scanning probe techniques is particularly well-suited for the microscopic study of these properties. We have developed a scanning probe microscope (SPM) which is capable of both standard force imaging (atomic, magnetic, electrostatic) and simultaneous electrical transport measurements. We utilize flexible and inexpensive FPGA (field-programmable gate array) hardware and a custom software framework developed in National Instrument's LabVIEW environment to perform the various aspects of microscope operation and device measurement. The FPGA-based approach enables sensitive, real-time cantilever frequency-shift detection. Using this system, we demonstrate electrostatic force microscopy of an electrically biased graphene field-effect transistor device. The combination of SPM and electrical transport also enables imaging of the transport response to a localized perturbation provided by the scanned cantilever tip. Facilitated by the broad presence of LabVIEW in the experimental sciences and the openness of our software solution, our system permits a wide variety of combined scanning and transport measurements by providing standardized interfaces and flexible access to all aspects of a measurement (input and output signals, and processed data). Our system also enables precise control of timing (synchronization of scanning and transport operations) and implementation of sophisticated feedback protocols, and thus should be broadly interesting and useful to practitioners in the field.

Fast ellipsometric measurements based on a single crystal photo-elastic modulator

For quality control in high volume manufacturing of thin layers and for tracking of physical and chemical processes, ellipsometry is a common measurement technology. For such kinds of applications we present a novel approach of fast ellipsometric measurements. Instead of a conventional setup that uses a standard photo-elastic modulator, we use a 92 kHz Single Crystal Photo-Elastic Modulator (SCPEM), which is a LiTaO3 crystal with a size of 28 × 9 × 4 mm. This small, simple, and cost-effective solution also offers the advantage of direct control of the retardation via the current amplitude, which is important for repeatability of the measurements. Instead of a Lock-In Amplifier, an automated digital processing based on a fast analog to digital converter controlled by a highly flexible Field Programmable Gate Array is used. This and the extremely compact and efficient polarization modulation allow fast ellipsometric testing where the upper limit of measurement rates is mainly limited by the desired accuracy and repeatability of the measurements. The standard deviation that is related to the repeatability +/-0.002° for dielectric layers can be easily reached.

A Component-Based FPGA Design Framework for Neuronal Ion Channel Dynamics Simulations

Neuron-machine interfaces such as dynamic clamp and brain-implantable neuroprosthetic devices require real-time simulations of neuronal ion channel dynamics. Field-programmable gate array (FPGA) has emerged as a high-speed digital platform ideal for such application-specific computations. We propose an efficient and flexible component-based FPGA design framework for neuronal ion channel dynamics simulations, which overcomes certain limitations of the recently proposed memory-based approach. A parallel processing strategy is used to minimize computational delay, and a hardware-efficient factoring approach for calculating exponential and division functions in neuronal ion channel models is used to conserve resource consumption. Performances of the various FPGA design approaches are compared theoretically and experimentally in corresponding implementations of the alpha-amino-3-hydroxy-5-methyl-4-isoxazole propionic acid (AMPA) and N-methyl-D-aspartate (NMDA) synaptic ion channel models. Our results suggest that the component-based design framework provides a more memory economic solution, as well as more efficient logic utilization for large word lengths, whereas the memory-based approach may be suitable for time-critical applications where a higher throughput rate is desired.

From research to product using a common development platform

This paper describes a hardware and software platform used to develop prototypes of advanced instrumentation in a university research environment. It consists of a commercial processor board, running a real-time operating system, linked to analogue electronics via a highly flexible field-programmable gate-array (FPGA). The use of Handel-C to configure the FPGA means that the prototypes are essentially ‘software products’ and that the intellectual property created is readily ported to commercial applications using components with appropriate price, performance and power consumption. Two examples, from the process and transport industries, demonstrate how the platform can be used to move from research prototype to near-commercial product.