Flash-SAR ADC Research Articles

A 15-Bit 85 MS/s Hybrid Flash-SAR ADC in 90-nm CMOS

A 15-bit, 85 MS/s hybrid flash-SAR ADC is presented. The proposed design combines modified tri-level switching technique with split capacitor technique to improve the power efficiency and sampling rate of the SAR block. The sampling switch was designed to achieve reduced settling time for DAC. Modified encoder block was used in flash ADC block and PMOS resistive ladder was used for better matching and linearity. To overcome high-frequency noise jitters in resistive ladder, parallel capacitors were added which act as low-pass filter. At 85 MS/s device consumes 650 uW and achieved an SNDR of 74.3 dB, ENOB of 12.06 with SFDR of 89 dBc. The proposed ADC is implemented in 1P-9M low K 90-nm CMOS process technology and occupies a chip area of 720 um $$\times $$× 195 um.

A design of 10-bit, 10 MS/s Pipelined ADC with Time-interleaved SAR

This paper presents a 10-bit, 10MS/s pipelined ADC with a time-interleaved SAR. Owing to the shared multiplying-DAC between the flash ADC and the multi-channel-SAR ADC, the total capacitance of the SAR ADC is decreased by 93.75%. The proposed ADC architecture can therefore provide a higher resolution than the conventional time-interleaved flash-SAR ADC. The proposed 10-bit, 10 MS/s ADC achieves a 9.318-bit ENOB and a figure-of-merit of 357.11 fJ/conversion-step. The ADC that consumes 2.28mW under a supply voltage of 1.2V was fabricated in 0.13µm CMOS and occupies an area of only 0.21mm2.

A 4-Channel Multi-Rate VCSEL Driver with Automatic Power, Magnitude Calibration using High-Speed Time-Interleaved Flash-SAR ADC in 0.13 ㎛ CMOS

This paper presents a 4-channel multi-rate vertical-cavity surface-emitting laser (VCSEL) driver. In order to keep the output power constant with respect to the process, voltage, temperature (PVT) variations, this research proposes automatic power and magnitude. For the fast settling time, the high-speed 10-bit time-interleaved Flash-successive approximation analog to digital converter (Flash-SAR ADC) is proposed and shared for automatic power and magnitude calibration to reduce the die area and power consumption. This chip is fabricated using 0.13-μm CMOS technology and the die area is 4.2 mm². The power consumption is 117.84 mW per channel from a 3.3 V supply voltage at 10 Gbps. The measured resolution of bias /modulation current for APC/AMC is 0.015 mA.

Design of 10-bit 10MS/s Time-Interleaved Flash-SAR ADC Using Sharable MDAC

This paper presents a 10-bit 10 MS/s Time-Interleaved Flash-SAR ADC with a shared Multiplying DAC. Using shared MDAC, the total capacitance in the SAR ADC decreased by 93.75%. The proposed ADC consumed 2.28mW under a 1.2V supply and achieved 9.679 bit ENOB performance. The ADC was implemented in 0.13μm CMOS technology. The chip area was 760 × 280 μ㎡.