Flash Memory Controller Research Articles

Design and Integration of NAND Flash Memory Controller for Open Power-based Fabless SoC

NAND Flash Memory has replaced EEPROM and hard drives as Non-volatile. Data is stored in sequential order in NAND Flash Memory. NAND Memory is a type of flash memory widely used in mobile phones and System on Chips (SoC). The Memory controller supports an 8-bit NAND Flash interface and streaming interface towards АXI4. The data transfer between АXI4 and NAND Flash Memory is carried оut by using NAND Flash commands sequences. The AXI4 Interface enables the usage of various рrоtосоls. To improve the flash memory controller's data access speed. This project intends to design, develop, and integrate a NAND Flash memory controller using an AXI4 interface for an open POWER Processor A20 fabless SOC. The Flash Memory Controller includes Finite State Machines (FSM) and AXI4 bridge logic. Using Mentor Graphics® and Xilinx's Vivado design suite, the test results were based on behavioral simulation and synthesis

Achievable-Rate-Aware Retention-Error Correction for Multi-Level-Cell NAND Flash Memory

Owing to the effect of data retention noise in multi-level-cell NAND flash memory, the initial threshold-voltage distributions and read voltages can no longer be used to accurately calculate log-likelihood ratios (LLRs) as the retention time increases, thus causing retention errors. To solve this problem, we first utilize the so-called “correction factors” to optimize the LLR accuracy by maximizing the achievable rate of a flash-memory system without introducing extra memory-sensing operations. We further prove that the optimization of the correction factors is a convex optimization problem and can be solved analytically. To obtain the optimal correction factors, we propose two retention-error correction schemes, referred to as offline maximum-achievable-rate correction (MARC) algorithm and online MARC algorithm, which enable the flash-memory controller to utilize the corrected LLRs that are stored in a look-up table and correct the inaccurate LLRs in real time, respectively. Motivated by the variation characteristics of the threshold-voltage distributions, we also propose an enhanced expectation–maximization (EM) algorithm to reestimate their corresponding parameters, and then adjust the read voltages. By combining the enhanced EM algorithm with the MARC algorithms, an enhanced EM-based correction strategy is developed to further boost the retention-error endurance of flash memory while avoiding excessive memory-sensing overhead. Theoretical analyses and simulation results illustrate the superiority of the proposed correction mehtods in terms of the robustness against retention errors.

Experimental Evaluation of e.MMC Data Recovery

In this paper, we explore the data recovery procedures from e∙MMCs. The e∙MMC is one of the “managed” flash memory devices that are popularly used in modern digital devices as their storage media. The e∙MMC, which consists of flash memory and the flash memory controller, optimizes the data input/output between the host device and the non-volatile memory through its standardized protocol. Its standardized structure and protocol makes forensic physical data acquisition simpler than handling the raw flash memory. However, its secure data purging features, such as Secure Erase and Sanitize, make data recovery from e∙MMC a challenging task. In this research, we investigate inside the e∙MMCs, and evaluate advanced data recovery procedures. By reverse engineering the structures of e∙MMCs and accessing the internal flash memory, we discover that securely erased data is still recoverable from the internal flash memory. In some models, more than 99% of the securely erased data can still be recoverable by accessing the flash memory inside the e∙MMCs. The data extraction method, along with experimental data recovery evaluation, will be explored in this paper.

Interleaved Write Scheme for Improving Sequential Write Throughput of Multi-Chip MLC NAND Flash Memory Systems

Mass-storage systems made of multi-level cell (MLC) NAND flash memory are cost effective but suffer from limited sequential write throughput. Although conventional interleaved write scheme helps, the unique characteristic of the MLC that the write time of a least significant bit (LSB) is much shorter than that of a most significant bit (MSB) leaves performance improvement headroom. This article presents an interleaved write scheme for improving the sequential write throughput of the multi-chip MLC NAND flash memory system. It leverages the longer write time of the upper pages to transmit more data by reordering the interleaved write sequence of the MLC chips. The proposed scheme can be directly implemented in the firmware of the flash memory controller without conflicting with existing flash translation layer (FTL) routines. No hardware modification is needed. The design criteria and performance improvements of general MLC NAND flash storage systems are derived for optimizing the system’s performance. Experimental results of an example single-channel 4-chip solid-state drives (SSD) system showed the sequential write throughput was improved by over 11.4%. The proposed interleaved write scheme can be applied to multi-channel storage systems to improve their sequential write throughput as well.

Machine Learning for LLR Estimation in Flash Memory With LDPC Codes

As the density of flash memory is increasing to improve storage capacity, it also becomes more vulnerable to reading errors. Hence it is common practice to employ error-correcting codes, such as low-density parity check (LDPC) codes. To exploit the error-correcting capability of these codes, soft input must be provided to the decoder. This means that the flash memory controller needs to be able to provide reliability values, which is usually obtained through multiple `soft' reads of the cells in the form of log-likelihood ratios (LLR). However finding these reliabilities with high accuracy is not easy with very few reads. In this brief we present a novel approach to estimate the LLRs based on a previous idea by Sharon et al. for regular LDPC codes. We present a low-complexity solution using machine learning and also an extension to irregular LDPC codes. A neural network is trained with offline data (simulated or measured) for a wide range of operating conditions and can then be applied to flash memory readings. By simulations we show that this provides good performance with only a small loss compared with genie-aided LLRs.

Compression-Assisted Adaptive ECC and RAID Scattering for NAND Flash Storage Devices.

NAND flash memory-based storage devices are vulnerable to errors induced by NAND flash memory cells. Error-correction codes (ECCs) are integrated into the flash memory controller to correct errors in flash memory. However, since ECCs show inherent limits in checking the excessive increase in errors, a complementary method should be considered for the reliability of flash storage devices. In this paper, we propose a scheme based on lossless data compression that enhances the error recovery ability of flash storage devices, which applies to improve recovery capability both of inside and outside the page. Within a page, ECC encoding is realized on compressed data by the adaptive ECC module, which results in a reduced code rate. From the perspective of outside the page, the compressed data are not placed at the beginning of the page, but rather is placed at a specific location within the page, which makes it possible to skip certain pages during the recovery phase. As a result, the proposed scheme improves the uncorrectable bit error rate (UBER) of the legacy system.

Machine-Learning-Based Read Reference Voltage Estimation for NAND Flash Memory Systems Without Knowledge of Retention Time

To achieve a low error rate of NAND flash memory, reliable reference voltages should be updated based on the accurate knowledge of program/erase (P/E) cycles and retention time, because those severely distort the threshold voltage distribution of memory cell. Due to the sensitivity to the temperature, however, a flash memory controller is unable to acquire the exact knowledge of retention time, meaning that it is challenging to estimate accurate read reference voltages in practice. In this article, we propose a novel machine-learning-based read reference voltage estimation framework for the NAND flash memory systems without the knowledge of retention time. To establish an unknown input-output relation of the estimation model, we derive input features by sensing and decoding memory cells in the minimum read unit. In order to define the relation between unlabeled input features and a pre-assigned class label, namely label read reference voltages, we propose three mapping functions: 1) $k$ -nearest neighbors-based, 2) nearest-centroid-based, and 3) polynomial regression-based read reference voltage estimators. For the proposed estimation schemes, we analyze that the storage overhead and computational complexity are increasing function of the exploited feature dimension. Accordingly, we propose a feature selection (or dimension reduction) algorithm to select the minimum dimension and corresponding features to reduce the overhead and complexity while maintaining high estimation accuracy. Based on extensive numerical analysis, we validate that the derived features successfully replace unknown knowledge of retention time, and the proposed feature selection algorithm precisely adjusts the trade-off between overhead/complexity and estimation accuracy. Furthermore, the simulation and analysis results show that the proposed framework not only outperforms the conventional estimation schemes but also achieves the near-optimal frame error rate while sustaining low latency performance.

Recovering SQLite data from fragmented flash pages

As a small-sized database engine, SQLite is widely used in embedded devices, such as mobile phones and PDAs. Large amounts of sensitive personal data are stored in SQLite. Any unintentional data deletion or unexpected device damage can cause considerable loss to the owners of the data. Therefore, in these cases, it is necessary to be able to recover and extract SQLite data records from the flash memory of portable devices. However, most existing SQLite recovery studies take the database file as the research subject, while it is not possible to acquire an intact database file when the flash memory controller is damaged. This paper presents a new method to recover SQLite data records from fragmented flash pages. Instead of investigating the whole *.db file or the journal file, the suggested method focuses on the analysis of B-Tree leaf page structure, which is the basic storage unit, to locate and extract existing and deleted data records based on the structures of the page header and cells in the leaf page, and then uses the SQLite_master structure to translate hex data records into meaningful SQLite tables. The experimental results show that this new method is effective regardless of which file system is used.

When Flash Failure is not an Option

The tension between cost and reliability is driving the development of flash-memory controllers that can support critical embedded applications. The New Electronics team reports

Area-Optimized Fully-Flexible BCH Decoder for Multiple GF Dimensions

Recently, there are increasing demands for fully flexible Bose–Chaudhuri–Hocquenghem (BCH) decoders, which can support different dimensions of Galois fields (GF) operations. As the previous BCH decoders are mainly targeting the fixed GF operations, the conventional techniques are no longer suitable for multiple GF dimensions. For the area-optimized flexible BCH decoders, in this paper, we present several optimization schemes for reducing hardware costs of multi-dimensional GF operations. In the proposed optimizations, we first reformulate the matrix operations in syndrome calculation and Chien search for sharing more common sub-expressions between GF operations having different dimensions. The cell-based multi-m GF multiplier is newly introduced for the area-efficient flexible key-equation solver. As case studies, we design several prototype flexible BCH decoders for digital video broadcasting systems and NAND flash memory controllers managing different page sizes. The implementation results show that the proposed fully-flexible BCH decoder architecture remarkably enhances the area-efficiency compared with the conventional solutions.

Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives

NAND flash memory is ubiquitous in everyday life today because its capacity has continuously increased and cost has continuously decreased over decades. This positive growth is a result of two key trends: 1) effective process technology scaling; and 2) multi-level (e.g., MLC, TLC) cell data coding. Unfortunately, the reliability of raw data stored in flash memory has also continued to become more difficult to ensure, because these two trends lead to 1) fewer electrons in the flash memory cell floating gate to represent the data; and 2) larger cell-to-cell interference and disturbance effects. Without mitigation, worsening reliability can reduce the lifetime of NAND flash memory. As a result, flash memory controllers in solid-state drives (SSDs) have become much more sophisticated: they incorporate many effective techniques to ensure the correct interpretation of noisy data stored in flash memory cells. In this article, we review recent advances in SSD error characterization, mitigation, and data recovery techniques for reliability and lifetime improvement. We provide rigorous experimental data from state-of-the-art MLC and TLC NAND flash devices on various types of flash memory errors, to motivate the need for such techniques. Based on the understanding developed by the experimental characterization, we describe several mitigation and recovery techniques, including 1) cell-to-cell interference mitigation; 2) optimal multi-level cell sensing; 3) error correction using state-of-the-art algorithms and methods; and 4) data recovery when error correction fails. We quantify the reliability improvement provided by each of these techniques. Looking forward, we briefly discuss how flash memory and these techniques could evolve into the future.

On Die Bit Error Rate Estimator for NAND Flash Memory

In this brief, we propose a simple bit error rate (BER) estimator utilizing the parity check constraints of a low-density parity-check code-based error correction coding (ECC) scheme. The proposed estimator can be efficiently implemented on flash memory die with a very small area cost. We articulate applications in which flash memory controllers can take advantage of having the BER estimate before the ECC decoding scheme to significantly reduce programming errors and improve system performance in terms of latency and throughput.

Performance and Reliability Analysis of Cross-Layer Optimizations of NAND Flash Controllers

NAND flash memories are becoming the predominant technology in the implementation of mass storage systems for both embedded and high-performance applications. However, when considering data and code storage in Non-Volatile Memories (NVMs), such as NAND flash memories, reliability and performance become a serious concern for systems designers. Designing NAND flash-based systems based on worst-case scenarios leads to waste of resources in terms of performance, power consumption, and storage capacity. This is clearly in contrast with the request for runtime reconfigurability, adaptivity, and resource optimization in modern computing systems. There is a clear trend toward supporting differentiated access modes in flash memory controllers, each one setting a differentiated tradeoff point in the performance-reliability optimization space. This is supported by the possibility of tuning the NAND flash memory performance, reliability, and power consumption through several tuning knobs such as the flash programming algorithm and the flash error correcting code. However, to successfully exploit these degrees of freedom, it is mandatory to clearly understand the effect that the combined tuning of these parameters has on the full NVM subsystem. This article performs a comprehensive quantitative analysis of the benefits provided by the runtime reconfigurability of an MLC NAND flash controller through the combined effect of an adaptable memory programming circuitry coupled with runtime adaptation of the ECC correction capability. The full NVM subsystem is taken into account, starting from a characterization of the low-level circuitry to the effect of the adaptation on a wide set of realistic benchmarks in order to provide readers a clear view of the benefit this combined adaptation may provide at the system level.

A visual approach to interpreting NAND flash memory

The research described in this paper proposes methods for visually interpreting the content of raw NAND flash memory images into higher level visual artefacts of assistance in reverse engineering and interpreting flash storage formats. A novel method of reverse engineering the structure and layout of individual memory locations within NAND flash images, based on injecting a known signal into a test NAND environment is also proposed. Omissions in the current theory of operation of flash, in particular the role of flash memory controllers in transforming the raw NAND are identified, clarifying the cause of variations seen between images taken using pseudo physical and raw physical techniques. The effectiveness of the approach is validated against raw NAND images from YAFFS2 based Android phones, taken via JTAG and chip-off methods.

A CONFIGURABLE BOSE–CHAUDHURI–HOCQUENGHEM CODEC ARCHITECTURE FOR FLASH CONTROLLER APPLICATIONS

Error correction coding (ECC) has become one of the most important tasks of flash memory controllers. The gate count of the ECC unit is taking up a significant share of the overall logic. Scaling the ECC strength to the growing error correction requirements has become increasingly difficult when considering cost and area limitations. This work presents a configurable encoding and decoding architecture for binary Bose–Chaudhuri–Hocquenghem (BCH) codes. The proposed concept supports a wide range of code rates and facilitates a trade-off between throughput and space complexity. Commonly, hardware implementations for BCH decoding perform many Galois field multiplications in parallel. We propose a new decoding technique that uses different parallelization degrees depending on the actual number of errors. This approach significantly reduces the number of required multipliers, where the average number of decoding cycles is even smaller than with a fully parallel implementation.

An Efficient Copy-Back Operation Scheme Using Dedicated Flash Memory Controller in Solid-State Disks

An Efficient Copy-Back Operation Scheme Using Dedicated Flash Memory Controller in Solid-State Disks

FPGA-Based Flash Memory Controller for BZK.SAU.FPGA10.1 Microcomputer Architecture Design as an Educational Tool

FPGA-Based Flash Memory Controller for BZK.SAU.FPGA10.1 Microcomputer Architecture Design as an Educational Tool

Ozone (O3): An Out-of-Order Flash Memory Controller Architecture

Ozone (O3) is a flash memory controller that increases the performance of a flash storage system by executing multiple flash operations out of order. In the O3 flash controller, data dependencies are the only ordering constraints on the execution of multiple flash operations. This allows O3 to exploit the multichip parallelism inherent in flash memory much more effectively than interleaving. The O3 controller also provides a prioritized handling of flash operations, equipping flash management software, such as the FTL (flash translation layer), with control knobs for managing flash operations of different time criticalities. Running a range of workloads on an FPGA implementation showed that the O3 flash controller achieves 3 to 100 percent more throughput than interleaving, with 46 to 88 percent lower response times.

FTL algorithms for NAND-type flash memories

Flash memory is being rapidly deployed as data storage for embedded devices such as PDAs, MP3 players, mobile phones and digital cameras due to its low electronic power, non-volatile storage, high performance, physical stability and portability. The most prominent characteristic of flash memory is that prewritten data can only be dynamically updated via the time consuming erase operation. Furthermore, every block in flash memory has a limited program/erase cycle. In order to manage these issues, the flash memory controller can be integrated with a software module called the flash translation layer (FTL). This paper surveys the state-of-art FTL algorithms. The FTL algorithms can be classified by the complexity of the algorithms: basic and advance. Furthermore, they can be classified by their corresponding tasks: performance enhancement and durability enhancement. The FTL algorithms corresponding to each classification are further broken down into various schemes depending on the methods they adopt. This paper also provides the information of hardware features of flash memory for FTL programmers.

Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD)

As the cell size of the NAND flash memory has been scaled down by 40%-50% per year and the memory capacity has been doubling every year, a solid-state drive (SSD) that uses NAND as mass storage for personal computers and enterprise servers is attracting much attention. To realize a low-power high-speed SSD, the co-design of NAND flash memory and NAND controller circuits is essential. In this paper, three new circuit technologies, the selective bit-line precharge scheme, the advanced source-line program, and the intelligent interleaving, are proposed. In the selective bit-line precharge scheme, an unnecessary bit-line precharge is removed during the verify-read and consequently the current consumption decreases by 23%. In the advanced source-line program scheme, a hierarchical source-line structure is adopted. The load capacitance during the program pulse is reduced by 90% without a die size overhead. As a result, the current consumption is reduced by 48%. Finally, with the intelligent interleaving, a current peak is suppressed and a high-speed parallel write operation of the NAND flash memories is achieved. By using these three technologies, both the NAND flash memory and the NAND controller circuits are best optimized. At the sub-30 nm generation, the current consumption of the NAND flash memory decreases by 60% and the SSD speed improves by 150% without a cost penalty or circuit noise.