Flash Memory Based Storage Systems Research Articles

Exploiting Uncorrectable Data Reuse for Performance Improvement of Flash Memory

With the increased density and the technology scaling, flash memory is more vulnerable to noise effects, overwhelmingly lowering the data retention time. The periodic data refresh technique is commonly used to retain the long-term data integrity. However, the frequent refresh requests introduce the increased access conflict and severe write amplification, leading to suboptimal performance and lifetime improvement of flash memory-based storage systems. In this article, we propose ApproxRefresh, which enables the uncorrectable data reuse with the assistance of approximate-computing applications to reduce the refresh costs. Specifically, we design a lightweight remapping-free refresh technique, called RFR, to periodically correct, compute an enhanced ECC, and only remap new ECC parity bits, which dramatically reduces the refresh costs. Then, with approximate-read and precise-read hotness awareness, ApproxRefresh selectively adopts RFR or the traditional remapping-based refresh technique to reduce the refresh costs and the read disturbance. Besides, ApproxRefresh further improves flash access performance based on data hotness and process variations. In addition, a corresponding ApproxRefresh-aware garbage collection algorithm is proposed to complete the design. Evaluations show that ApproxRefresh reduces the refresh latency by 36.19% over the state of the art.

Building Reliable Massive Capacity SSDs through a Flash Aware RAID-Like Protection

The demand for mass storage devices has become an inevitable consequence of the explosive increase in data volume. The three-dimensional (3D) vertical NAND (V-NAND) and quad-level cell (QLC) technologies rapidly accelerate the capacity increase of flash memory based storage system, such as SSDs (Solid State Drives). Massive capacity SSDs adopt dozens or hundreds of flash memory chips in order to implement large capacity storage. However, employing such a large number of flash chips increases the error rate in SSDs. A RAID-like technique inside an SSD has been used in a variety of commercial products, along with various studies, in order to protect user data. With the advent of new types of massive storage devices, studies on the design of RAID-like protection techniques for such huge capacity SSDs are important and essential. In this paper, we propose a massive SSD-Aware Parity Logging (mSAPL) scheme that protects against n-failures at the same time in a stripe, where n is protection strength that is specified by the user. The proposed technique allows for us to choose the strength of protection for user data. We implemented mSAPL on a trace-based simulator and evaluated it with real-world I/O workload traces. In addition, we quantitatively analyze the error rates of a flash based SSD for different RAID-like configurations with analytic models. We show that mSAPL outperforms the state-of-the-art RAID-like technique in the performance and reliability.

A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems

Toward the aim of realizing high-bandwidth, large-capacity nand flash memory-based storage systems, this paper presents a novel daisy-chain downlink interface (I/F) between a controller and a large number of nand packages. The daisy-chain I/F employs a tapered-bandwidth architecture with bridge-by-bridge data extraction based on a proposed spectrally compressed multi-band multiplexing (SCM2) technique to achieve low power consumption. By using the proposed downlink I/F, a nand controller can handle 32 low-cost nand packages while achieving 12.8-Gb/s throughput using two data wires. The fabricated prototype downlink I/F achieved a bit error rate (BER) of 10−12 with power consumption of 252.1 mW for the transmitter and 375.7 mW for all four receivers together.

Asymmetric Error Rates of Cell States Exploration for Performance Improvement on Flash Memory Based Storage Systems

Recent studies show that a multilevel cell flash cell in different states suffers from diverse error patterns in varying degrees. That is, the error rates of each page are highly dependent on the data content. Consequently, pages with different data will exhibit quite different error rates. However, existing technologies equipped with one uniform error correction code (ECC) scheme for all pages in a flash memory do not take the different error rates of pages into consideration. In this paper, we propose to exploit the asymmetric error rates of flash memory exhibited by the flash pages with different data for performance improvement. Before a page is programmed, its specific error rates, called content-dependent bit error rates (CDBERs), are estimated according to the content of the page. The margin between the CDBER of a page and the maximal error rates correctable by the uniform ECC code is exploited for performance improvement. On one hand, a faster and suitable write operation is selected to speed up the progress of programming while the increased speed induced CDBER does not exceed the maximal correctable error rates. On the other hand, a light-weight ECC scheme can be chosen for a faster read operation since the page decoding process of a light-weight ECC scheme incurs less time overhead. Finally, a state mapping scheme, which further reduces the CDBER through mapping high error rate states to the low error rate states of a page, is proposed. Simulation results show that the proposed approaches lead to significant write and read performance improvement.

Balancing Spatial Locality with Parallelism in Solid State Disks

Objectives: Modern flash memory based storage systems, such as Solid State Disks (SSDs), are actively utilizing the channel/way interleaving to exploit parallelism among multiple NAND chips. Methods/Statistical Analysis: However, the flip side of the interleaving is that it disperses data with spatial locality across different NAND blocks, which eventually causes a high garbage collection overhead. To overcome this problem, we propose a spatial locality-aware allocation policy, called SLAP. It uses the notion of stream, which is defined as a set of data having consecutive Logical Page Numbers (LPN). Findings: By allocating a stream into a NAND block separately, it can preserve the spatial locality. In addition, by handling multiple streams simultaneously, it can obtain the parallelism among NAND chips. Also, we discuss that SLAP can balance between locality-preserving and parallelism by providing a spectrum from a traditional parallelism-oriented allocation to a strict locality-preserving one. We have implemented SLAP on a page-level mapping Flash Translation Layer (FTL) that is being used as a default FTL in many commercial SSDs. Improvements/Applications: Trace-driven simulation based experimental results have shown that SLAP can improve performance by up to 35.3% with an average of 13.1%, compared with the traditional allocation policy for the three workload considered.

H-Hash: A Hash Index Structure for Flash-Based Solid State Drives

Flash-based solid state drives (SSDs) have been widely used as storage medium because of their fast access speed, high reliability and low power consumption. In spite of these advantages, they inherit distinct characteristics such as no in-place updates, asymmetric operation speed and unit because they consist of NAND flash memories. Therefore, a disk-based hash index structure may result in severe performance degradation if it is directly deployed on a NAND flash memory-based storage system. In this paper, we propose a new hybrid hash index structure for flash-based SSDs. It delays and reduces the split operations which cause slow block erasure and additional read and write operations by exploiting overflow buckets according to the ratio of updates and deletions. Through various performance evaluations, we show the superiority of our proposed index structure by comparing it to other hash index structures for flash-based SSDs.

Extending lifetime of flash memory using strong error correction coding

Demand for flash memory based storage systems is on the rise because flash memory has many advantages when compared with hard disk drives, such as lower latency and resistance to physical shock. However, flash memory permits only a limited number of program/erase (P/E) cycles, and after the guaranteed number of P/E cycles, data cannot be reliably retrieved due to uncorrectable errors. Given a target bit error rate, the guaranteed number of P/E cycles decreases as more bits are stored in one cell and as the cell size is scaled down. In this paper, a novel lifetime extension mechanism for flash memory, referred to as a gradual error correction code (GECC), is proposed. A G-ECC provides a stronger level of error correction than a standard ECC by sacrificing a small portion of storage capacity in order to store additional parity bits. The proposed method can extend the lifetime of flash memory by 124% at the cost of a 12% loss in capacity. The use of additional parity bits necessarily leads to performance loss due to increased accesses for those additional parity bits and garbage collection operations involving those bits. Thus, methods to alleviate such performance loss are proposed; these methods reduce the performance overhead from 17% (without the proposed methods) to 3% even in the worst case.

LSB-Tree: a log-structured B-Tree index structure for NAND flash SSDs

NAND flash memory has been widely used as a storage device for embedded systems because of its fast access speed, low power consumption, and lower noise compared to a hard disk. However, due to its unique characteristics such as the lack of an in-place update and asymmetric operation speed/unit, conventional disk-based systems and applications may experience severe performance degradation when NAND flash memory is used. When a disk-based index structure such as a B-Tree is implemented in flash memory-based storage systems, intensive overwrite operations, which are caused by record insertion, deletion, and reorganization, may result in severe performance degradation. Although several index structures have been proposed to overcome this problem, they suffer from frequent node splits, rapid increments of tree height, and poor space usage. In this paper, we propose a log-structured B-Tree index structure where a log node corresponding to a leaf node is allocated for updating the modified data, and then these data in the log node are stored in a single write operation. Our proposed index structure reduces additional write operations by deferring parent node changes. In addition, the index structure reduces the number of write operations by directly switching the log node to a leaf node if the data are sequentially inserted according to key order. Through various experiments, we show that our proposed index structure performs better than related techniques.

Modeling the aging process of flash storage by leveraging semantic I/O

The major advantages of flash memory such as small physical size, no mechanical components, low power consumption, and high performance have made it likely to replace the magnetic disk drives in more and more systems. Many research efforts have been invested in employing flash memory to build high performance and large-scale storage systems for data-intensive applications. However, the endurance cycle of flash memory has become one of the most important challenges in further facilitating the flash memory based systems. This paper proposes to model the aging process of flash memory based storage systems constructed as a Redundant Array of Independent Disks (RAID) by leveraging the semantic I/O. The model attempts to strike a balance between the program/erase cycles and the rebuilding process of RAID. The analysis results demonstrate that a highly skewed data access pattern ages the flash memory based RAID with an arbitrary aging rate, and a properly chosen threshold of aging rate can prevent the system from aging with a uniform data access pattern. The analysis results in this paper provide useful insights for understanding and designing effective flash memory based storage systems.

LSF: a new buffer replacement scheme for flash memory-based portable media players

A portable media player is a consumer electronics device that is capable of storing and playing digital media such as audio, image, video, and etc. NAND flash memory has been widely deployed as a storage medium for these portable media players because of its small size, light weight and low power consumption. However, due to distinct characteristics of NAND flash memory such as no in-place update, asymmetric operation unit and speed, conventional disk-based buffer replacement scheme may not yield good performance on flash memory-based storage systems. In this work, we propose a novel buffer replacement scheme considering the features of metadata as well as multimedia data for portable media players. Our proposed scheme classifies the pages into a long sequential reference set and a short sequential reference set by checking the sequential continuity of pages in the buffer. And then, it mainly evicts long sequential reference sets first from the buffer and keeps short sequential reference sets in the buffer as long as possible to improve the hit ratio. By this strategy, we can efficiently reduce the number of write and erase operations to the flash memory when storing and playing digital media. Through various experiments, we show that our proposed scheme yields better performance than its related work <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sup> .

A technique to improve garbage collection performance for NAND flash-based storage systems

Garbage collection (GC) is a time-consuming operation incorporated in flash memory storage systems, and thus, it has a significant impact on the storage performance. Flash memory provides an internal copy-back operation that can perform page data transfer efficiently during GC. However, this operation is not widely accepted due to some limitations: bit errors can be propagated during the transfer between the pages without being detected, and the operation can be used for blocks within the same plane. In order to address these problems, the page data must be read to a buffer and then transmitted to another page. When this method is used, not only does a temporal overhead occur but also I/O bus utilization and power consumption by the two data transfer operations are increased. In this paper, we propose a technique for reducing the data transfer overhead of GC, using which devices transmit data directly when garbage is collected in a flash memory-based storage system in which several flash memory devices share a single I/O bus, while only the partial updated corrected data is updated when an error is detected. The proposed technique improves the performance of GC and reduces I/O bus utilization compared to the existing methods.

FeGC: An efficient garbage collection scheme for flash memory based storage systems

NAND flash memory is a promising storage media that provides low-power consumption, high density, high performance, and shock resistance. Due to these versatile features, NAND flash memory is anticipated to be used as storage in enterprise-scale systems as well as small embedded devices. However, unlike traditional hard disks, flash memory should perform garbage collection that consists of a series of erase operations. The erase operation is time-consuming and it usually degrades the performance of storage systems seriously. Moreover, the number of erase operations allowed to each flash memory block is limited. This paper presents a new garbage collection scheme for flash memory based storage systems that focuses on reducing garbage collection overhead, and improving the endurance of flash memory. The scheme also reduces the energy consumption of storage systems significantly. Trace-driven simulations show that the proposed scheme performs better than various existing garbage collection schemes in terms of the garbage collection time, the number of erase operations, the energy consumption, and the endurance of flash memory.

Architectures and optimization methods of flash memory based storage systems

Flash memory is a non-volatile memory which can be electrically erased and reprogrammed. Its major advantages such as small physical size, no mechanical components, low power consumption, and high performance have made it likely to replace the magnetic disk drives in more and more systems. However, flash memory has four specific features which are different to the magnetic disk drives, and pose challenges to develop practical techniques: (1) Flash memory is erased in blocks, but written in pages. (2) A block has to be erased before writing data to the block. (3) A block of flash memory can only be written for a specified number of times. (4) Writing pages within a block should be done sequentially. This survey presents the architectures, technologies, and optimization methods employed by the existing flash memory based storage systems to tackle the challenges. I hope that this paper will encourage researchers to analyze, optimize, and develop practical techniques to improve the performance and reduce the energy consumption of flash memory based storage systems, by leveraging the existing methods and solutions.

NAND 플래시 메모리 기반의 대용량 저장장치 설계

During past 20 years we have witnessed brilliant advances in major components of computer system, including CPU, memory, network device and HDD. Among these components, in spite of its tremendous advance in capacity, the HDD is the most performance dragging device until now and there is little affirmative forecasting that this problem will be resolved in the near future. We present a new approach to solve this problem using the NAND Flash memory. Researches utilizing Flash memory as storage medium are abundant these days, but almost all of them are targeted to mobile or embedded devices. Our research aims to develop the NAND Flash memory based storage system enough even for enterprise level server systems. This paper present structural and operational mechanism to overcome the weaknesses of existing NAND Flash memory based storage system, and its evaluation.

Performance Trade-Offs in Using NVRAM Write Buffer for Flash Memory-Based Storage Devices

While NAND flash memory is used in a variety of end-user devices, it has a few disadvantages, such as asymmetric speed of read and write operations, inability to in-place updates, among others. To overcome these problems, various flash-aware strategies have been suggested in terms of buffer cache, file system, FTL, and others. Also, the recent development of next-generation nonvolatile memory types such as MRAM, FeRAM, and PRAM provide higher commercial value to non-volatile RAM (NVRAM). At today's prices, however, they are not yet cost-effective. In this paper, we suggest the utilization of small-sized, next-generation NVRAM as a write buffer to improve the .overall performance of NAND flash memory-based storage systems. We propose various block-based NVRAM write buffer management policies and evaluate the performance improvement of NAND flash memory-based storage systems under each policy. Also, we propose a novel write buffer-aware flash translation layer algorithm, optimistic FTL, which is designed to harmonize well with NVRAM write buffers. Simulation results show that the proposed buffer management policies outperform the traditional page-based LRU algorithm and the proposed optimistic FTL outperforms previous log block-based FTL algorithms, such as BAST and FAST.

A flash compression layer for SmartMedia card systems

Flash memory based SmartMedia card is becoming increasingly popular as data storage for mobile consumer electronics. Since flash memory is an order of magnitude more expensive than magnetic disks, data compression can be effectively used in managing flash memory based storage systems. However, compressed data management in flash memory is challenging because it only supports page-based I/Os. For example, when the size of compressed data is smaller than the page size, internal fragmentation occurs and this degrades the effectiveness of compression seriously. In this paper, we developed a flash compression layer (FCL) for the SmartMedia card systems. FCL stores several small compressed pages into one physical page by using a write buffer. Based on prototype implementation and simulation studies, we show that the proposed system offers the storage of flash memory more than 140% of its original size and expands the write bandwidth significantly.