Fixed-point Math Research Articles

Implementation of VLSI on Signal Processing-Based Digital Architecture Using AES Algorithm

Continuous improvements in very-large-scale integration (VLSI) technology and design software have significantly broadened the scope of digital signal processing (DSP) applications. The use of application-specific integrated circuits (ASICs) and programmable digital signal processors for many DSP applications have changed, even though new system implementations based on reconfigurable computing are becoming more complex. Adaptable platforms that combine hardware and software programmability efficiency are rapidly maturing with discrete wavelet transformation (DWT) and sophisticated computerized design techniques, which are much needed in today’s modern world. New research and commercial efforts to sustain power optimization, cost savings, and improved runtime effectiveness have been initiated as initial reconfigurable technologies have emerged. Hence, in this paper, it is proposed that the DWT method can be implemented on a field-programmable gate array in a digital architecture (FPGA-DA). We examined the effects of quantization on DWT performance in classification problems to demonstrate its reliability concerning fixed-point math implementations. The Advanced Encryption Standard (AES) algorithm for DWT learning used in this architecture is less responsive to resampling errors than the previously proposed solution in the literature using the artificial neural networks (ANN) method. By reducing hardware area by 57%, the proposed system has a higher throughput rate of 88.72%, reliability analysis of 95.5% compared to the other standard methods.

Development design and demonstration of very high‐speed multi‐antenna digital receiver

The authors present initial results from the fourth-generation receiver for the Manastash Ridge radar, which is a distributed passive radar system used for ionospheric physics and engineering studies. This receiver permits simultaneous access to the high-frequency (HF), very HF (VHF), and ultra HF (UHF) spectrum by sampling at speeds up to 5 billion samples/s on multiple antennas. This system has large aggregate bandwidth; it can simultaneously collect the entire VHF FM broadcast band as well as several UHF DTV broadcasts. The receiver adopts direct sampling architecture; therefore, high dynamic range is achieved with decimation for narrowband signals. Most of the analogue signal path is eliminated, yielding excellent linearity, and high-speed digital signal processing in the field programmable gate array (FPGA) yields low-latency real-time operation. The authors also discuss algorithms to make effective use of the FPGA. For example, the sampler runs 16 times faster than the FPGA, so initial FPGA processing requires parallel algorithms. In the authors design, the downconverter passband centre frequencies and spectral widths are selectable at run time, and can be changed in a few milliseconds. The authors FPGA computes in fixed point math, which presents both opportunities and challenges in managing precision during the signal processing for networking and for subsequent signal processing.

DSP를 이용한 부스트 컨버터의 전류 제어기 설계 및 구현

This paper introduces a method for design and implementation of a current controller for boost converter operating in continuous conduction mode (CCM) using a digital signal processor (DSP). A Proportional-Integral (PI) type current controller outputs an average voltage command for inductor, used in the input side of the boost converter, and the duty-ratio of PWM (pulse width modulation) signal for switching device is directly calculated from the average voltage command. The gains of the PI current controller are selected such that the current response characteristics are the same as those of a first-order low-pass filter. The proposed current control scheme is implemented using a DSP based on fixed-point math operations and an experimental study has been performed to validate the proposed method.

Design of an FPGA-Based Algorithm for Real-Time Solutions of Statistics-Based Positioning

We report on the implementation of an algorithm and hardware platform to allow real-time processing of the statistics-based positioning (SBP) method for continuous miniature crystal element (cMiCE) detectors. The SBP method allows an intrinsic spatial resolution of ~1.6 mm FWHM to be achieved using our cMiCE design. Previous SBP solutions have required a postprocessing procedure due to the computation and memory intensive nature of SBP. This new implementation takes advantage of a combination of algebraic simplifications, conversion to fixed-point math, and a hierarchal search technique to greatly accelerate the algorithm. For the presented seven stage, 127 × 127 bin LUT implementation, these algorithm improvements result in a reduction from >7 × 10(6) floating-point operations per event for an exhaustive search to < 5 × 10(3) integer operations per event. Simulations show nearly identical FWHM positioning resolution for this accelerated SBP solution, and positioning differences of <0.1 mm from the exhaustive search solution. A pipelined field programmable gate array (FPGA) implementation of this optimized algorithm is able to process events in excess of 250 K events per second, which is greater than the maximum expected coincidence rate for an individual detector. In contrast with all detectors being processed at a centralized host, as in the current system, a separate FPGA is available at each detector, thus dividing the computational load. These methods allow SBP results to be calculated in real-time and to be presented to the image generation components in real-time. A hardware implementation has been developed using a commercially available prototype board.

A digital architecture for support vector machines: theory, algorithm, and fpga implementation

In this paper, we propose a digital architecture for support vector machine (SVM) learning and discuss its implementation on a field programmable gate array (FPGA). We analyze briefly the quantization effects on the performance of the SVM in classification problems to show its robustness, in the feedforward phase, respect to fixed-point math implementations; then, we address the problem of SVM learning. The architecture described here makes use of a new algorithm for SVM learning which is less sensitive to quantization errors respect to the solution appeared so far in the literature. The algorithm is composed of two parts: the first one exploits a recurrent network for finding the parameters of the SVM; the second one uses a bisection process for computing the threshold. The architecture implementing the algorithm is described in detail and mapped on a real current-generation FPGA (Xilinx Virtex II). Its effectiveness is then tested on a channel equalization problem, where real-time performances are of paramount importance.

Digital VLSI algorithms and architectures for support vector machines.

In this paper, we propose some very simple algorithms and architectures for a digital VLSI implementation of Support Vector Machines. We discuss the main aspects concerning the realization of the learning phase of SVMs, with special attention on the effects of fixed-point math for computing and storing the parameters of the network. Some experiments on two classification problems are described that show the efficiency of the proposed methods in reaching optimal solutions with reasonable hardware requirements.

Digital VLSI Algorithms and Architectures for Support Vector Machines

In this paper, we propose some very simple algorithms and architectures for a digital VLSI implementation of Support Vector Machines. We discuss the main aspects concerning the realization of the learning phase of SVMs, with special attention on the effects of fixed-point math for computing and storing the parameters of the network. Some experiments on two classification problems are described that show the efficiency of the proposed methods in reaching optimal solutions with reaonable hardware requirements.