Fixed Pattern Noise Compensation Research Articles

A 2 kfps Sub-µW/Pix Uncooled-PbSe Digital Imager With 10 Bit DR Adjustment and FPN Correction for High-Speed and Low-Cost MWIR Applications

Mid-wavelength infrared (MWIR) thermography is an emerging technology with promising applications such as industrial monitoring, medicine and automotive, but its use in high-speed cameras is not yet widespread due to the lack of inexpensive sensor integration solutions and their common reliance on bulky cooling mechanisms. This work fills the gap by presenting a monolithic uncooled high-speed imager based on vapor-phase deposition lead selenide (VPD PbSe) photoconductors and a fully digital and configurable CMOS read-out integrated circuit (ROIC) to operate the MWIR imager. This ROIC features cancellation of PbSe dark current, compensation of its output capacitance and correction of the fixed pattern noise (FPN) caused by process non-uniformities in CMOS fabrication and detector deposition. The low-cost 80 × 80 imager has been integrated using 0.35 µm 2P4M standard CMOS technology and PbSe detector post-processing with 135 µm pixel pitch and 68% fill factor values. Experimental opto-electrical performance exhibits 10 bit real-time FPN compensation and DR calibration over the entire focal plane operating at 2 kfps, sub-0.5 LSB inter-pixel crosstalk, sub-µW pixel power consumption, and an overall figure of merit of 55 mK × ms.

Precise FPN compensation circuit for CMOS APS

Fixed pattern noise (FPN) is one of the major disadvantages of CMOS imagers in comparison with CCD imagers. A simple and precise FPN compensation circuit for a CMOS active pixel sensor (APS) imager with in-line non-destructive readout function is presented.