Fixed-head Disk Research Articles

Evolution and implementations of the RAP database machine

The article presents the evolution of the RAP. 1, RAP. 2, and RAP. 3 database architectures and discusses various implementations carried out to date. The RAP database machine has evolved from a fixed head disk based SIMD architecture into one that is an MIMD architecture and optimized around solid state bulk memories. With the dynamic and order preserving data space partitioning strategy, binary relational algebra and projection operation complexity has been reduced to a linear order. Its tagging based universal language has enabled various system implementations such as multimodel support, integrated text retrieval capabilities, and security and integrity control.

The effects of solid state paging devices in a large time-sharing system

This paper reports the results of some measurements taken on the effects two new solid state paging devices, the STC 4305 and the Intel 3805, have on paging performance in the Michigan Terminal System at the University of Michigan. The measurements were taken with a software monitor using various configurations of the two solid state devices and the fixed head disk, which they replace. Measurements were taken both during regular production and using an artificial load created to exercise the paging subsystem. The results confirmed the expectation that the solid state paging devices provide shorter page-in waiting times than the fixed-head disk, and also pointed up some of the effects which their differing architectures have on the system.

The Multi-Processor Process Computer System Employing a Data Way Used at the Yawata No. 3 Steelmaking Plant

In 1979, a multi-processor process computer system using a data way was installed at the No. 3 steelmaking plant of Yawata Works, Nippon Steel Corporation.The system includes five central processing units (CPUs), a common core memory unit, eight fixed-head disk units and peripherals in a single computer room. Ten remote stations including four intelligent stations are connected to the CPUs through a data way. Process input-output units and man-machine interface units are connected mainly to the remote stations.This paper presents a review of the system mainly from the viewpoint of the systems structural technology by comparing it with a conventional system for an existing steel plant. A discussion is made of the benefits and problems in relation to the requirements for high availability, simple data management, small initial cost, easy testing, expandability, etc.

The multi-processor process computer system employing a data way used at the Yawata No. 3 steelmaking plant

In 1979, a multi-processor process computer system using a data way was installed at the No. 3 steelmaking plant of Yawata Works, Nippon Steel Corporation. The system includes five central processing units (CPUs), a common core memory unit, eight fixed-head disk units and peripherals in a single computer room. Ten remote stations including four intelligent stations are connected to the CPUs through a data way. Process input-output units and man-machine interface units are connected mainly to the remote stations. This paper presents a review of the system mainly from the viewpoint of the systems structural technology by comparing it with a conventional system for an existing steel plant. A discussion is made of the benefits and problems in relation to the requirements for high availability, simple data management, small initial cost, easy testing, expandability, etc.

New Products

Dataram's BC-303 bulk core system emulates Data General's 6063/6065 fixedhead disk system. The disk emulation system for Nova, Supernova, and Eclipse minicomputers is compatible with Data General's Advanced Operating System, Real-time Disk Operating System, and 6063/6065 FHD diagnostics and can use either the standard or high-speed data channel interface.

Flexible real-time nuclear data acquisition processing software

A computer program for nuclear data acquisition is described which performs “incremental linking” of the memory-resident data-processing software modules according to console keyboard commands. The modules perform functions associated with pulse-height analysis. This technique allows a single program to adapt to many experimental situations and allows an experimenter to change his data acquisition program during an experiment. On-line processing of arbitrary complexity is possible. After outlining the data acquisition software framework, the paper discusses details of the data acquisition processor, and an example of its use is given. A critique discusses shortcomings of the first release of the program. An appendix describes an algorithm for updating histograms on a fixed-head disk in real time.

The Implications of Electronic Serial Memories*

Advances in such new memory technologies as charge-coupled devices, magnetic bubble memories, and beam access memories have opened avenues for innovative applications of these computer elements in future computing systems. These quasi-serial electronic technologies compete on one hand with the random access memories (bipolar, MOS, and core) and, on the other hand, with disk memories (fixed-head disk and moving-head disk). There are important functional properties common to all these technologies, and their applications as computer memories will depend upon how successfully the systems designers appreciate–and then apply–these characteristics to computer system design.

Fixed-head disk memory unit for high reliability applications : I. Isozaki, H. Matsumotor, O. Miyazaki, M. Ito, S. Nakamura, S. Yamamura, S. Kageyama, S. Mitsuashi and K. Nakamura. NEC Res. Dev.44, 57 (January 1977)

Fixed-head disk memory unit for high reliability applications : I. Isozaki, H. Matsumotor, O. Miyazaki, M. Ito, S. Nakamura, S. Yamamura, S. Kageyama, S. Mitsuashi and K. Nakamura. NEC Res. Dev.44, 57 (January 1977)

Special Tutorial: The Organization of Electronic Cyclic Memories

Cyclic memories are memories in which data rotate cyclically past a read/write port. The most common cyclic memories in use today are mechanical drums and fixed-head disks. In the past, small electronic cyclic memories have been made from MOS technology; more recently they have been made from charge-coupled devices and magnetic bubbles. Because of advances in integrated technology, large electronic cyclic memories that might be replacements for drum and disk memories are likely to become available. Whereas it is difficult to predict what technology will eventually emerge for electronic auxiliary memories, present projections suggest that cyclically organized memories based upon magnetic bubbles or charge-coupled devices are potential candidates. The disadvantage of cyclic organization is that access time due to memory latency may be excessive. The problem we investigate in this paper is how to modify electronic cyclic memories in relatively minor and inexpensive ways so as to decrease rotational latency in a system environment.

Response Time of a Fixed-Head Disk to Transfers of Variable Length

Due to the practical complexity of addressing variable length records placed in arbitrary locations of a fixed-head disk (or drum), and because of difficulty of managing secondary memory space in such cases, variable length records are often stored with their first address at a fixed location of the magnetic support. We present a queuing model of such a scheme, assuming a Poisson arrival stream and arbitrary distributed record lengths. The stationary probability distribution of the number of transfer requests in queue and the expected response time are obtained. Numerical examples illustrating the results are presented.

A Generalization of Eklundh's Algorithm for Transposing Large Matrices

The purpose of this paper is to present an algorithm for transposing large rectangular matrices. This is basically a generalization of Eklundh's algorithm. Eklundh's method is designed to handle arrays in place of using powers-of-2 approach wherein partitions of the matrix have dimensions which are powers of 2. The algorithm presented here does not have this restriction. The choice of partitions is posed as an optimal control problem amenable to solution using Bellman's principle of optimality. The optimal partitioning of the matrix can be determined depending on the computer configuration (i.e., core size, whether moving-head or fixed-head disk drives are used, number of words per track, etc.) and the matrix dimensions. Simple modifications are noted for transposing complex/double precision and packed integer matrices. Experimental results are presented comparing the times needed for transposition using optimal partitioning and powers-of-2 partitioning. It is found in the cases tested that a speed gain of up to 5.55 is obtained by optimizing the partition sizes.

Tutorial: Computer System Advantages of Magnetic Bubble Memories

Magnetic bubbles, which offer improved access time over most conventional fixed-head disks, are now serious contenders for memory applications in computer systems. Current literature abounds in descriptions of various technological advances that have led to experimental memory systems.1,2,3Bubble memory chips containing up to 20,510 bits per chip have been exercised through transfer-read-transfer-circulate cycles in good loops at 100 KHz data rate.1An overview of current technology capabilities and a look into the future have been presented by H. Chang.4

8192-bit block addressable CCD memory

Design data and experimental characteristics are given on an 8192-bit n-channel charge-coupled memory device, intended for applications requiring shorter latency than ordinary MOS shift registers or fixed-head disks and at potentially lower cost than either MOS shift registers or random-access memories. This was achieved by dividing the array into 32 memory blocks of 256 bits each, with addressable, random access to any block, permitting average latency of approximately 100 /spl mu/s. A two-level overlapping polysilicon gate process was used, with conservative design tolerances. Power dissipation on-chip, plus capacitive drive power during data access at 1 MHz is approximately 250 mW, and less than 5 mW during standby at 20 kHz with data retention.

A multiline computer voice response system utilizing ADPCM coded speech

In this paper we discuss the issues involved in implementing an automatic computer voice response system which is capable of serving up to ten independent output channels in real time. The system has been implemented on a Data General NOVA- 800 minicomputer. Individual isolated words and phrases are coded at a rate of 24 000 bits/s using a hardware adaptive, differential pulse-code modulation (ADPCM) coder, and stored on a fixed-head disk as a random access vocabulary. By exploiting the features of ADPCM coding, it is possible to create and edit automatically a vocabulary for the system from an analog tape recording of the spoken entries, with minimal operator intervention. To provide ten simultaneous output lines of speech which are independent of each other required the use of an efficient scheduling algorithm. Such an algorithm was provided by the computer manufacturer in their real-time multitasking system which was part of their Fortran software. Thus almost all the programming required to implement this real-time system was in Fortran, thereby providing flexibility and ease in making changes in the system. Initial applications of the voice response system are in computer aided voice wiring, automatic directory assistance, and experiments on speaker verification, but the system is sufficiently modular to adapt readily to other applications.

A Multiline Computer Voice Response System Utilizing ADPCM Coded Speech

An automatic voice response system is described which is capable of servicing up to ten independent output channels in real time. The system is implemented on a NOVA 800 minicomputer. Individual words and phrases are coded at a 24 000 bits/sec rate using adaptive, differential pulse-code modulation (ADPCM) techniques, and are stored on a fixed-head disk as a random-access vocabulary. The system was designed so that it is possible to create a new vocabulary for the system automatically from an analog tape recording with minimal operator intervention. Initial applications of the system are in computer-aided voice wiring and automatic directory assistance.

Analyse d'un algorithme de gestion simultan�e m�moire centrale ? disque de pagination

Commonly used memory management strategies in a paged environment optimize separately the page-fault rate (by proper choice of a replacement algorithm) and the response time of the paging drum (by a shortest-access-time-first discipline with multiple sectors). In this paper we consider replacement strategies which attempt to maximize useful CPU utilisation and hence throughput by choosing the page to be replaced on the basis of its probability of reference as well as on the rapidity with which the page can be removed from main memory, assuming that a fixed-head disk or drum is used as a secondary memory. An analysis of the approach is given using a mathematical model. Analytical results for the gain in CPU utilisation are obtained under mono-programming and numerical examples are presented illustrating the effects of variation of program behaviour and of variants of the replacement strategy.

An Optimal Drum Scheduling Algorithm

Suppose a set of N records must be read or written from a drum, fixed-head disk, or similar storage unit of a computer system. The records vary in length and are arbitrarily located on the surface of the drum. The problem considered here is to find an algorithm that schedules the processing of these records with the minimal total amount of rotational latency (access time), taking into account the current position of the drum. This problem is a special case of the traveling salesman problem. The algorithm that is developed has the attractive property of exhibiting a computational complexity on the order of N log N.

A real-time multiuser foreground, single-user background system for the PDP-9 computer

We have developed a software system for a PDP-9, with fixed head disk, to allow up to 16 remote laboratories to use the central PDP-9 facility for their experimental data acquisition and control needs. Timesharing is performed on a “demand” basis, using the hardware automatic priority-interrupt option. The real-time acquisition and control aspects are separated from the data reduction in the foreground by using a batch process foreground mainstream. The background is used primarily as a systems device for program updates and communications with a CDC terminal connected to a CDC 6600 computer. The philosophy, both software and hardware, developed for this heterogeneous user environment will be discussed.

Orela Data Acquisition into Greater than 105 Channels through a Priority Multiplexer Operating on a Direct Memory Access and a Program Controlled Device Interface

The Oak Ridge Electron Linear Accelerator (ORELA) facility includes a linear accelerator and a series of computers for real-time data acquisition and on-line analysis of the acquired data. The unique features of the data acquisition computers are the following: a word-addressed, fixed-head disk; a direct-memory access, four-channel priority multiplexer capable of a peak data rate of 25,000 events/sec per channel; and a program-controlled, subaddressed device interface. Operation of the word-addressed, fixed-head disk through software and hardware control allows the experimental events to determine which channels are to have their contents read into the core memory from the disk for updating, with a resulting theoretical maximnum average data rate of 11,000 events/sec. Trade-offs for future systems are possible between the hardware and software. Operation of the priority multiplexer is described briefly. A modified, TMC, 4096-channel time-of-flight analyzer allows control from the computer through the multiplexer. A pulse generating unit, mounted in a triple-width NIM module, operates through one channel of the program-controlled device interface to control a TMC time-of-flight analyzer and a sample changer. The sample changer operates in a feedback loop that is controlled by a computer program.

Optimizing the Performance of a Drum-Like Storage

This paper analyzes the performance, for a particular strategy, of a head-per-track type auxiliary storage system in a real-time environment. The prototype system of either fixed-head disks or drums incorporates a hardware queuer. This device attempts to always select first that request for a data transfer which will incur the shortest rotational latency relative to all other possible waiting file access requests. The queueing analysis is concerned with the tradeoff which is experienced in practice between throughput of a stochastic service device and the response time for each service request. An exact analysis of the system is shown to be totally unmanageable. Therefore, the approach is to estimate the results via physical arguments. We obtain an approximate stationary distribution for the waiting time of a file access request in the system.