Five-level Cascaded H-bridge Inverter Research Articles

A Novel Multiobjective Finite Control Set Model Predictive Control for IPMSM Drive Fed by a Five-Level Cascaded H-Bridge Inverter

A Novel Multiobjective Finite Control Set Model Predictive Control for IPMSM Drive Fed by a Five-Level Cascaded H-Bridge Inverter

HERIC-Based Cascaded H-Bridge Inverter for Leakage Current Suppression in PV Systems

Leakage current can flow through the transformerless photovoltaic (PV) systems because of no galvanic isolation. This undesirable current results in more losses, electromagnetic interferences, and total harmonic distortion. This article presents a hardware-based method to suppress the leakage current in transformerless cascaded H-bridge (CHB) based PV systems. The proposed scheme uses high-efficient and reliable inverter concept in CHB converters for the first time. Using this idea and proper utilization of ac-side filters leads to leakage current suppression in individual cells and, thus, the whole system. In contrast to the most existing solutions, the proposed technique can be easily extended to CHB inverters with an arbitrary number of voltage levels. Moreover, this solution is applicable in the system's conditions with unequal parasitic capacitances and unequal dc-link voltages of H-bridge cells. The validity of the proposed solution is verified by several simulations in the PSCAD/EMTDC environment. Then, the experimental results on a five-level CHB inverter are presented to confirm the theoretical and simulation results.

Dead-Time Impact on the Harmonic Distortion and Conversion Efficiency in a Three-Phase Five-Level Cascaded H-Bridge Inverter: Mathematical Formulation and Experimental Analysis

To avoid leg short-circuit in inverters, dead time must be introduced on leg gate signals. Dead time affects the inverter output voltage fundamental harmonic amplitude, voltage harmonic distortion and inverter efficiency by introducing additional voltage drops. In this regard, dead time effects have been widely investigated for traditional two-level three-phase voltage source inverters in the literature but not extensively for multilevel topology structures. This paper provides a detailed analysis of dead time impact on the harmonic distortion and efficiency of Cascaded H-Bridges Multilevel Inverters (CHBMIs). For this purpose, a general mathematical formulation to determine voltage drop due to dead time effects, also taking into account the adopted Multicarrier PWM strategy, has been provided and experimentally validated for a five-level three-phase CHBMI structure. As a comparison tool between expected and ideal inverter output voltage, the percentage voltage error <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e</i> % is introduced. In most of the cases, <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">e</i> % is lower than 5%, and it starts increasing for very low amplitude modulation index or for specific working points where nonlinearities occur. Furthermore, several experimental investigations have been carried out to evaluate the CHBMI performance in terms of harmonic distortion and efficiency by changing, the values of dead time, modulation index and switching frequency for ten different multi-carried PWM strategies. Experimental results confirm the strong dependency between the dead time impact on the converter performance and the adopted Multi Carrier-PWM (MC-PWM) strategy: as a way of example, converter efficiency can be reduced from 80% to 60% when dead time is increased from 0.5 μs to 1.5 μs and Phase Shifted-PWM (PS-PWM) is adopted.

Power Quality Improvement Meeting Important Grid Codes Using Three-Phase Five-Level CHB Inverter With Improved Quarter and Half-Wave Symmetry Based Optimized SHM-PAM

Selective harmonic minimization-pulse amplitude modulation (SHM-PAM) scheme suppresses more number of selected voltage harmonic components of a predefined voltage waveform pattern for a wider range. This article presents formulations of some improved five-level pulse patterns based on both quarter-wave symmetry (QWS) and half-wave symmetry (HWS) with a low number of switching instants using the optimized SHM-PAM scheme to meet the CIGRE WG36-05/EN 50160 and IEC 61000-3-6 grid codes. The switching angles and normalized value of dc voltage sources are calculated by the recently reported dragonfly algorithm based optimization technique. The performance of the proposed schemes has been verified through simulation and experimentation on a three-phase five-level cascaded H-bridge (CHB) inverter. A comparison between the proposed two types of formulations has been carried out based on various aspects, such as waveform quality, dc power conversion capability, and power loss in the power semiconductor devices of the CHB inverter and efficiency. It is observed that QWS formulations exhibit better waveform quality than the HWS formulations sacrificing the efficiency of CHB inverter due to higher switching losses. Moreover, the effectiveness of the proposed schemes has been compared with some prior conventional modulation schemes.

Leakage Current Suppression in Multilevel Cascaded H-Bridge Based Photovoltaic Inverters

The transformerless inverters are more attractive due to their higher efficiency, lower cost, and lighter weight for grid-tied photovoltaic (PV) systems. However, the leakage current can flow through the system because of no galvanic isolation. This undesirable current leads to more losses, electromagnetic interferences, current harmonic distortion, and safety concerns. Therefore, the suppression of the leakage current in transformerless cascaded H-bridge (CHB) based PV systems is investigated in this article. First, the theoretical analysis is presented to model the leakage current for a five-level CHB inverter, and then a new modulation-based method is proposed to suppress this current. In contrast to most existing solutions, the proposed method can be easily generalized through the series connection of five-level CHB blocks. The validity of the proposed solution is verified by several simulations in the power systems computer aided design (PSCAD)/EMTDC environment. Then, experimental results on a five-level and nine-level CHB inverter are presented to confirm the theoretical and simulation results.

Active Disturbance Rejection Control for a Five-Level Cascaded H-Bridge Inverter Fed Induction Motor Sensorless Field-Oriented

In this paper, a robust vector control sensorless based on three Active Disturbance Rejection Controllers (ADRC) for an induction motor fed by a five-level cascaded H-bridge was developed. The estimation of rotor position is achieved using a Luenberger estimator. The proposed model considers the disturbances and the inaccuracies of the system and compensates them using the extended state observer of ADRC. Moreover, a five-level cascaded H-bridge inverter is the best topology to minimize the torque ripples and to improve the current output of IMunder control. The suggested control system was simulated under different conditions using MATLAB-Simulink. The results demonstrate the effectiveness and the robustness of the proposed system against disturbances such as variations of parameters and load torque.

The optimization of torque ripple reduction by using DTC-multilevel inverter

Direct Torque Control (DTC) scheme introduces a robust and simple control of electrical drive. However, its shortcomings such as broad torque ripple and variable switching frequency have offered several improvements like Space Vector Modulation (SVM) strategy, multilevel inverter (MLI) topology, etc. The conventional DTC which is fed by the two-level inverter has limited voltage vector, results in some difficulties to optimize the operation, especially at low operating speed. In contrast to MLI, the abundant of voltage vector has provided various amplitudes and angles that can overcome the problem of conventional DTC. Thus, this paper introduces the selected optimal voltage vector obtained from five-level Cascaded H-Bridge (CHB) inverter that employs in DTC hysteresis-based to achieve better optimization that similar to the DTC-SVM. Initially, the research work begins with an investigation on the performance comparison between a DTC hysteresis-based between two-level inverter (conventional method) and a five-level CHB inverter (proposed method). Here, a DC generator acted as a load is employed to control the operating speed instead of the speed controller (speed controller is negligible). Hence, the DTC method is optimized by minimizing the torque ripple as well as retaining the torque control capability at constant torque region on several operating speed. The selected optimal vector from the look-up table DTC of five-level CHB inverter must be dynamically appropriate to any change of torque (increased or decreased torque). For simplicity, this paper will only discuss the experimental results for both topologies of drive system. From the experimental results, it is verified that the torque ripples by the proposed method have achieved 10% and 50% reduction at high and low operating speed respectively. It is found that the DTC hysteresis-based result simpler control method than DTC-SVM while maintaining similar output performance.

Improved SHM‐PAM‐based five‐level CHB inverter to fulfil NRS 048‐2:2003 grid code and to apply as shunt active power filter with tuned proportional‐resonant controller for improving power quality

This study proposes a selective harmonic minimisation-pulse amplitude modulation (SHM-PAM) technique utilising least number of switching based on optimised waveform pattern for five-level cascaded H-bridge (CHB) inverter to satisfy the NRS 048-2:2003 grid code standard. Here, particle swarm optimisation method is used to evaluate the solution of the optimised switching angles and variable DC-link voltages. A comparison between the proposed SHM-PAM and conventional selective harmonic elimination-pulse width modulation (SHE-PWM) techniques has been carried out by harmonic performance analysis (total harmonic distortion (THD), weighted current THD and harmonic loss factor) and loss analysis (conduction, switching and their cumulative losses) of the switches of five-level CHB inverter under different load power factor angles for medium-voltage application. The performances of the conventional SHE-PWM and proposed SHM-PAM techniques are examined through experimentation using a three-phase five-level CHB inverter. Finally, the proposed technique based 5-level CHB inverter is applied to shunt active power filter using tuned proportional plus parallel resonant current controller for improvement in power quality under non-ideal grid conditions.

Experimental Validation of a Novel Method for Harmonic Mitigation for a Three-Phase Five-Level Cascaded H-Bridges Inverter

In modern high-power electrical drives, the efficiency of the system is a crucial constraint. Moreover, the efficiency of power converters plays a fundamental role in modern applications requiring also a limited weight, such as the electric vehicles and novel more electric aircraft. The reduction of losses pushes for systems with a dc bus and a high number of dc/ac converters, widespread in the vehicle, not burdened by a too expensive data processing system. The purpose of this article is to concur to reduce losses by proposing an innovative selective harmonic mitigation method based on the identification of the working areas where the reference harmonics present lower amplitudes. In particular, the main objective is to find a new way to calculate the control angles in real-time operation without solving nonlinear equations, whose resolution would require expensive controllers. Through a very simple approach, the polynomial equations, which drive the control angles, were detected for a three-phase five-level cascaded H-bridge inverter and implemented in a digital system to real-time operation with a low computational cost. As a result, a comparison between the simulation and experimental behavior is presented. In the last part of this article, a real electric machine is driven by considering the appropriate working areas and current harmonics are also evaluated.

Experimental Evaluation of the Performance of a Three-Phase Five-Level Cascaded H-Bridge Inverter by Means FPGA-Based Control Board for Grid Connected Applications

Over the last decades, plants devoted to the generation of green energy significantly increased their number, together with the demand of same electrical energy, also stored in battery systems. This fact produced the growth of energy conversion systems with advanced performances with respect to the traditional ones. In this circumstance, multilevel converters play a significant role for their great advantages in performances, flexibility, fault-tolerability, employment of renewable energy sources and storage systems and finally yet importantly reduced filter requirements. In this context, this paper faces the performance of a cascaded H-bridge 5 level inverter in terms of harmonic distortion generated and injected into the grid. Through an accurate analysis that takes into account the pulse width modulation (PWM) multicarrier modulation techniques (phase disposition PD, phase opposition disposition POD, alternative phase opposition disposition APOD, phase shifted PS) and related reference signals (sinusoidal reference; third harmonic injection THI reference, switching frequency optimal SFO reference), a framework of distorting harmonics is presented by comparing twelve cases. The results obtained from the simulations are reproduced and validated in a prototype system of five level cascaded H-bridge multilevel inverter. A deep discussion of control and filtering system is provided to justify the choice of the best modulation technique to adopt.

A Novel Non-Linear Control for Three-Phase Five-Level Cascaded H-Bridge Inverter Based Shunt Active Power Filter

Abstract Cascaded H-Bridge multilevel inverter (CHB-MLI) based shunt active power filter (SAPF) provides a cost-worthy and realistic solution for mitigating current related power quality problems in case of medium-voltage and high-power grid. Mitigation of current harmonic component, reactive power minimization and power factor correction depend on accuracy of control technique applied to the CHB-MLI based SAPF unit. Switching technique dynamics is not considered by most of the researchers while designing control techniques applied to SAPF unit and hence it is assumed linear in order to make system simpler. A limited amount of literature is available which considers the non-linearity of CHB-MLI switching pattern while designing control theory for MLI based SAPF. Therefore, a novel non-linear control is proposed in this paper to enhance system steady-state and dynamic performance. This non-linear control is based on dynamic mathematical modeling of five-level CHB-MLI tied SAPF. Stability of proposed control strategy applied to CHB-MLI based SAPF is rigorously checked by using Lyapunov’s direct method. Proportional-Integral controller is used for stabilizing DC-link voltages to its proper reference value. This proposed control exhibits excellent dynamic performance and compensation criteria in comparison to conventional control techniques available in the literature. The effectiveness of the proposed control theory is tested rigorously in MATLAB/Simulink and verified through hardware prototype under steady-state and transient operating conditions. Rigorous analysis from hardware and simulation results confirms that source current waveform is in compliance with IEEE-519 standard defined THD limit.

Modified Synchronous Vector Control Design of Multilevel Inverters for AC Grid Applications

This article presents a modified synchronous vector control design of a five-level cascaded H-Bridge inverter for integration of distributed generation (DG) resources to the power grid. The presented control strategy explores the limitations in the conventional synchronous vector control algorithm of grid-connected converter (GCC). The dynamic reference point (DRP) approach is considered to improve the performance of GCC. Compared with conventional control algorithm, DRP based control algorithm exhibits several specific advantages, such as increased reliability of the grid-interfaced converter, more active and reactive power injection capacity of the converter, and reduced cost of the converter. The objectives of control technique of the DG interface system are also employed to enhance the standard of the power grid. The optimized space vector pulse-width modulation (OSVPWM) control technique is used for grid integration. The simulation and experimental results are presented in order to validate the proposed functionalities of the grid-interfaced DG system. The effectiveness of the proposed control scheme is validated with better utilization of DG system, faster dynamics with reduced total harmonic distortion, better power factor, compensated load reactive power, and fault withstanding capability.

Random nearest level modulation strategy of multilevel cascaded H‐bridge inverters

Power converters using deterministic pulse width modulation (PWM) schemes have discrete and high harmonics concentrated at well-defined frequencies. In this study, two random PWM strategies to reduce the harmonic spikes for multilevel cascaded H-bridge (CHB) inverters are proposed. The proposed strategies select two nearest voltage levels to approximate output voltage based on simple geometrical calculations and randomly vary the pulse position of output voltage by choosing a random output instant of two nearest levels. The first proposed strategy provides two discrete pulse positions and one of them is selected by a random bit. The continuous varying of pulse position is generated in the second strategy, where a random interval varying from zero to sampling period is used to delay the beginning instant of pulse position. A maximum degree of freedom can be achieved in the second proposed strategy with lower harmonic spikes but higher commutation frequency, in comparison with the first strategy. A five-level CHB inverter controlled by TMS320F28335 DSP is tested and the experimental results compared with the deterministic PWM strategy validate the proposed strategies.

Five-level Cascaded H-Bridge Inverter with Predictive Current Control

This paper presents different kinds of grid-tied cascade H-bridge inverter and has a look to predictive current control technique. Finally the simulation result will show a Model predictive current control of a five-level cascaded H-bridge (CHB) inverter indifferent sampling times by using MATLAB Simulink software. And this Model Predictive current controller (MPC) for the five-level CHB inverter times has been created to display Total Harmonic Distortion (THD) level of the load and reference current pursuing for a step change with different sampling frequencies.

Optimized Space Vector Pulse-width Modulation Technique for a Five-level Cascaded H-Bridge Inverter

This paper presents an optimized space vector pulse-width modulation (OSVPWM) technique for a five-level cascaded H-bridge (CHB) inverter. The space vector diagram of the five-level CHB inverter is optimized by resolving it into inner and outer two-level space vector hexagons. Unlike conventional space vector topology, the proposed technique significantly reduces the involved computational time and efforts without compromising the performance of the five-level CHB inverter. A further optimized (FOSVPWM) technique is also presented in this paper, which significantly reduces the complexity and computational efforts. The developed techniques are verified through MATLAB/SIMULINK. Results are compared with sinusoidal pulse-width modulation (SPWM) to prove the validity of the proposed technique. The proposed simulation system is realized by using an XC3S400 field-programmable gate array from Xilinx, Inc. The experiment results are then presented for verification.

Model Predictive Current Control of a Five-level Cascaded HBridge Inverter with different Sampling Times

Model predictive current control of a five-level cascaded H-bridge (CHB) inverter with different sampling times is presented in this paper. The purpose of the current controller is to regulate the load current within the set reference current. A simulation model of the five-level CHB inverter with Model Predictive current controller (MPC) has been built to demonstrate the CHB inverter system performance in terms of Total Harmonic Distortion (THD) level of the load current and reference current tracking for a step change with different sampling times. The simulation results are observed by using the MATLAB Simulink software to validate the proposed current control technique.

Modeling, Simulation and Harmonic Reduction of Three-Phase Multilevel Cascaded Inverters with SVPWM for Photovoltaic System

This paper presents a control for a three-phase an eleven-level cascaded H-bridge inverter for photovoltaic (PV) system. The maximum power point tracking (MPPT) is capable of extracting maximum power from the PV array connected to each DC link voltage level. The MPPT algorithm is solved by fuzzy logic controller. Space vector pulse width modulation (SVPWM) algorithm uses a simple mapping to generate gate signals for the inverter. This is done to achieve high dynamic performance with low total harmonic distortion (THD). The validity of the system is verified through MATLAB/Simulink and results are compared with three-phase three-level, five-level, seven-level and nine-level cascaded H-bridge inverter for PV system in terms of THD. Finally, simulation results are presented to verify the effectiveness and accuracy of the proposed system.

Modified space vector modulation for fault‐tolerant operation of multilevel cascaded H‐bridge inverters

In this study, fault-tolerant operation of multilevel cascaded H-bridge (CHB) inverters is presented and a novel switching strategy based on space vector modulation is proposed. A faulty power switch in high power converters can lead to expensive downtime, loss of productivity and increased costs. Various power switch faults and their influence on space vector diagram of CHB inverters are investigated. In the event of a fault, the output voltage of inverter is reduced and redundant switching states are used to generate balanced line-to-line voltages. By adding some devices to the basic structure, CHB inverter will operate with maximum achievable output voltage. Simulation and experimental results are shown for a five-level CHB inverter to validate the proposed modulation technique.

Hybrid cascaded H-bridge inverter with even power distribution and improved total harmonic distortion: analysis and experimental validation

For high-power applications, cascaded H-bridge (CHB) inverters are conventionally controlled by selective harmonic mitigation (SHM) strategy. This technique is applied to reduce the switching loss and the optimised switching angles are calculated to mitigate low-order harmonics at the output voltage. However, this strategy causes an uneven power distribution among the CHB cells. Also mitigating more harmonics needs more number of pulses and consequently higher switching frequency and dissipated power. This study proposes a new hybrid CHB inverter with optimised dc sources. Considering the optimisation of the CHB dc sources&apos; values along with the optimised switching angles, significant improvements such as mitigating more low-order harmonics, even power distribution among the CHB cells and reducing the switching loss are achieved. Analysis and simulations are carried out on a five-level CHB inverter. Experimental verifications also validate the simulation results. The results demonstrate that the new hybrid CHB inverter considerably improves the performance of the conventional SHM strategy.