First-order Sigma-delta Modulator Research Articles

A 100-Gb/s PAM-4 DSP in 28-nm CMOS for Serdes Receiver

This paper presents a dedicated digital signal process (DSP) for four pulse amplitude modulation (PAM4) SerDes receivers. It is targeted to implement data recovery and adaptive equalization under ultra-high-speed and large channel attenuation with a small area and high power efficiency. The DSP consists of a clock data recovery (CDR), a 16-tap feed forward equalizer (FFE), a 1-tap decision feedback equalizer (DFE), and an automatic adaptation engine. An adaptive least mean square (LMS) algorithm is utilized to make the system more intelligent in calculating tap coefficients of the FFE and DFE. To address the timing limitation associated with traditional digital DFE that cannot handle large amounts of parallel data at a high speed, speculative techniques and a customized 4-to-1 multiplexer (MUX) unit are employed to remove the summation time and reduce the selection time, respectively. A first-order sigma-delta modulator is used to replace the traditional moving average to calculate average voltages, which could prominently save the hardware resources and power consumption. Additionally, the influence of input quantization resolution on the equalization ability is analyzed. Implemented in a 28-nm CMOS, the DSP could compensate for up to 33-dB loss at 100 Gb/s with a power consumption of 7.22 pJ/bit.

Class-D Audio Amplifier using Sigma-Delta (ΣΔ) Modulator

Pulse width modulation and pulse density modulation are deemed to be main modulation techniques, even PDM could not emulate PWM, in terms of, basically, simplicity. PDM bitstream is encoded through sigma-delta modulation. Since sigma-delta modulation, compared to PWM, needs very high switching frequency and more complicated materials to compose circuits, it’s more difficult to design one. In this article we design a low-power class-D audio amplifier circuit where the analog signal is encoded into pulse density modulation (PDM) using a first-order sigma-delta (ΣΔ) modulator. The designed circuit is built using Orcad-PSpice and results are analyzed with Matlab. A second-order integrator, a voltage divider as a feedback loop are used to mitigate basically, THD and get high efficiency. The audio signal is passed to the EM speaker through a Butterworth low-pass filter. A low THD of less than 0.2 % is obtained comparing to similar circuits in the literature and a high efficiency of 92 % is achieved.

A fully differential switched‐capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications

A novel switched-capacitor integrator based programmable resolution analog to digital converter (ADC) architecture is proposed. The proposed hybrid ADC architecture can be switched between successive approximation register (SAR) and delta-sigma modulator (DSM) mode in 8-bit to 15-bit resolution. A mathematical relationship showing the effect of mismatch of capacitors on ADC linearity is derived. A fully differential folded cascode operational transconductance amplifier (OTA) operating in a weak inversion region is designed using gm/ID technique with programmable unity gain bandwidth and slew rate. The designed OTA offers 83 dB DC gain. The proposed ADC, designed and laid out in UMC 180 nm standard CMOS technology, occupies an area of 0.228 mm2. The ADC resolution is programmable from 8-bit to 15-bit using a 3-bit control bus (res[2 : 0]). The hybrid ADC operates in SAR mode from 8-bit to 11-bit resolutions and as the first-order DSM with a multi-bit quantizer in 12-bit to 15-bit resolutions. The dynamic performance of the proposed ADC is verified through post-layout simulations with a supply voltage of 1.8 V. It exhibits a signal-to-noise and distortion ratio of 45–86 dB and consumes a power of 0.86–98 μW across target resolutions (8–15 bits).

An Ultra-Low-Voltage VCO-Based ΔΣ Modulator Using Self-compensated Current Reference for Variation Tolerance

This paper introduces a voltage-controlled-oscillator-based (VCO-based) first-order delta-sigma (ΔΣ) modulator that uses a novel current reference to improve the robustness of the modulator at ultra-low operating voltages. The proposed current reference harnesses the difference in transistor characteristics between weak inversion and moderate inversion to generate residue voltage, which is a function of process and temperature variations. The current generated by the proposed reference is used to bias a fully differential VCO integrator and a feedback current digital-to-analog conversion in the delta-sigma modulator for variation tolerance. Test chips designed and fabricated in 65-nm CMOS technology operate successfully at 0.3 V and achieve SNDR of 56.1 dB across 10 kHz bandwidth while consuming only 510 nW of power. This corresponds to a state-of-the-art figure of merit of 49 fJ/conv.-step. Measurement results for the proposed current reference and the modulator also demonstrate 3 × and 20 × improvement in process and temperature variation tolerance, respectively, while operating at such low voltages.

Using a Second Order Sigma-Delta Control to Improve the Performance of Metal-Oxide Gas Sensors.

Controls of surface potential have been proposed to accelerate the time response of MOX gas sensors. These controls use temperature modulations and a feedback loop based on first-order sigma-delta modulators to keep constant the surface potential. Changes in the surrounding gases, therefore, must be compensated by average temperature produced by the control loop, which is the new output signal. The purpose of this paper is to present a second order sigma-delta control of the surface potential for gas sensors. With this new control strategy, it is possible to obtain a second order zero of the quantization noise in the output signal. This provides a less noisy control of the surface potential, while at the same time some undesired effects of first order modulators, such as the presence of plateaus, are avoided. Experiments proving these performance improvements are presented using a gas sensor made of tungsten oxide nanowires. Plateau avoidance and second order noise shaping is shown with ethanol measurements.

Second order sigma-delta control of charge trapping for MOS capacitors

This paper presents the circuit topology of a second order sigma-delta control of charge trapping for MOS capacitors. With this new topology it is possible to avoid the presence of plateaus that can be found in first-order sigma-delta modulators. Plateaus are unwanted phenomena in which the control is locked for a certain time interval (of unknown duration). In this case the control output is constant and therefore the controlled device is in fact in open-loop configuration. It is shown that the presence of plateaus is avoided in MOS capacitors using the proposed approach.

Theoretical study and demonstration of photonic asynchronous first-order delta-sigma modulator for converting analog input to NRZ binary output

Fil: Costanzo Caso, Pablo Alejandro. Consejo Nacional de Investigaciones Cientificas y Tecnicas. Centro Cientifico Tecnologico La Plata. Centro de Investigaciones Opticas (i); Argentina. Rose-Hulman Institute of Technology. Physics and Optical Engineering Department; Estados Unidos

Extended Noise Shaping in Sigma-Delta Modulator Using Cross-Coupled Paths

In this paper, combined with time-interleaving, noise coupling is used to achieve considerable improvement in the performance of sigma-delta modulator. Two types of noise-coupling, unextended and extended coupling, are presented for $N$ -path architecture based on first-order sigma-delta modulator which can enhance the effective order of noise shaping without significant overhead. In the general condition, the optimum coupling matrices are obtained analytically to achieve the desired noise shaping. It is also shown that the proposed $N$ -path first-order sigma-delta modulator provides $(2N-1)$ th-order noise shaping. However, the unextended coupling provides $N$ th-order. To verify the proposed method, the macro-level simulations show that third-order and fifth-order noise shaping were achieved in two-path and three-path first-order sigma-delta modulators with extended noise coupling, respectively. Likewise, the ADS software's simulation result of the switched-capacitor circuit implementation confirms the effectiveness of the proposed method.

A Delta–Sigma Interface Circuit for Capacitive Sensors With an Automatically Calibrated Zero Point

We present a low-complexity interface circuit for capacitive sensors that are integrated into sensor microsystems. To reduce hardware cost while keeping high resolution, a first-order delta-sigma modulator (DSM), which balances the charge from the capacitive difference between sense and reference capacitors with the charge from a fixed-quantity capacitor, is employed. A charge-mode digital-to-analog converter and a successive approximation register are utilized to automatically calibrate the zero point of the interface circuit, which may shift further than a dynamic range. A prototype circuit fabricated in a 0.35-μm CMOS process has an active area of 0.048 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Its DSM operates at a sampling frequency of 1 MS/s with an oversampling ratio of 128. Experiments show that this circuit can read a capacitive difference from -0.5 to +0.5 pF with a 0.49-fF resolution. A capacitive offset that causes the zero point to shift can be canceled in the range from -2 to 2 pF with a 31.25-fF resolution. Measured power consumption was 1.44 mW at a 3.3-V supply.

SOI Pixel Based on a Floating Body Partially Depleted MOSFET in a Delta-Sigma Loop

Standard techniques used for measuring the photocurrent of an SOI phototransistor have failed due to two main reasons: the first being the low signal-to-noise ratio and the second being the slow transient. In this paper, the partially depleted silicon on insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) has been used as a light intensity sensor. Using a novel technique of measurement enables us to embed this phototransistor in the delta-sigma loop. The presented circuits implement a first-order delta-sigma modulator with limited number of transistors maximizing the fill factor. Measured data show that the implemented pixels were sensitive to flux densities as low as 3 mW/m2 with a resolution of 7.5 bits.

Wireless Amperometric Neurochemical Monitoring Using an Integrated Telemetry Circuit

An integrated circuit for wireless real-time monitoring of neurochemical activity in the nervous system is described. The chip is capable of conducting high-resolution amperometric measurements in four settings of the input current. The chip architecture includes a first-order Delta Sigma modulator (Delta Sigma M) and a frequency-shift-keyed (FSK) voltage-controlled oscillator (VCO) operating near 433 MHz. It is fabricated using the AMI 0.5 microm double-poly triple-metal n-well CMOS process, and requires only one off-chip component for operation. Measured dc current resolutions of approximately 250 fA, approximately 1.5 pA, approximately 4.5 pA, and approximately 17 pA were achieved for input currents in the range of +/-5, +/-37, +/-150, and +/-600 nA, respectively. The chip has been interfaced with a diamond-coated, quartz-insulated, microneedle, tungsten electrode, and successfully recorded dopamine concentration levels as low as 0.5 microM wirelessly over a transmission distance of approximately 0.5 m in flow injection analysis experiments.

General Dynamics of Pulsed Digital Oscillators

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> The objective of this work is to analyze pulsed digital oscillators (PDOs), as dynamical systems. It is proved that under some conditions, the bitstream at the output of the oscillator is that of the sign of a sampled sinusoid at the resonant frequency of the resonator, and that a bijection exists between these sequences (without distinguishing between a sequence and its negated version) and those of first-order sigma-delta modulators. This provides a new and simple method of obtaining the oscillation frequency of PDOs just from their bitstream. </para>

Characterization of sigma–delta modulator with LR-type integrator for superconducting analog-to-digital converter

We studied the signal-to-noise ratios (SNRs) of a superconducting first-order sigma–delta modulator with an LR integrator. Effects of leakage in the LR integrator and thermal noise on SNR were investigated analyzing a transfer function and simulating circuits with thermal noise sources. Leakage resulted in a decrease in the SNR of 1.5dB and thermal noise in a decrease of 5.5dB, at a sampling frequency of 20GHz. We found that decreases in SNR due to leakage and thermal noise in a comparator were independent of the sampling frequency. Thermal noise in an integrating resistor on the other hand became dominant for a decrease in SNR at frequencies above 5GHz. We also designed a modulator and evaluated its SNRs experimentally. An SNR of 71dB was obtained at a sampling frequency of 10GHz. The dependency of SNR on sampling frequency was consistent with the simulated one. The present results indicate that transfer function analysis and circuit simulations with thermal noise can provide practical estimates of SNRs for modulators.

Characteristics of Superconducting First-Order Sigma-Delta Modulator With Clock-Doubler Circuit

Superconducting first-order sigma-delta modulator was designed and evaluated experimentally at the sampling frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> ) over 10 GHz using an internal clock-doubler circuit. We employed a complementary-feedback type first-order sigma-delta modulator with an LR integrator. The numerical simulation indicated that higher f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> of 20 GHz are required to achieve 14-bit resolution for the signal bandwidth of 10 MHz. We newly developed a frequency doubler circuit to generate 20 GHz clock signals from external 10 GHz signals. The modulator could be evaluated experimentally at f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">s</sub> up to 16 GHz, which limited by the measurement system. The measured SINAD (signal-to-noise-and-distortion ratio) of the modulator is almost equal to the numerically simulated value, and the SINAD at 16 GHz is about 77 dB for the signal bandwidth of 10 MHz.

Low-Voltage Current-Sensing CMOS Interface Circuit for Piezo-Resistive Pressure Sensor

A new low-voltage CMOS interface circuit with digital output for piezo-resistive transducer is proposed. An input current sensing configuration is used to detect change in piezo-resistance due to applied pressure and to allow lowvoltage circuit operation. A simple 1-bit first-order deltasigma modulator is used to produce an output digital bitstream. The proposed interface circuit is realized in a 0. 35 µm CMOS technology and draws less than 200 μA from a single 1.5 V power supply voltage. Simulation results show that the circuit can achieve an equivalent output resolution of 9.67 bits with less than 0.23% nonlinearity error.

Evaluation of superconducting first-order sigma-delta modulator

We designed and tested a superconducting first-order sigma-delta modulator for a superconductor/semiconductor hybrid-type analog-to-digital converter. The modulator has a complimentary negative feedback loop including a clocked inverter. Analog signal is introduced to the modulator with a transformer and an LR integrator is located in front of it. The performance of the modulator circuits was evaluated by the numerical simulation. The maximum signal-to-noise ratio (SNR) and spurious-free dynamic range (SFDR) for the signal bandwidth of 10MHz at the sampling frequency (fs) of 10GHz were estimated to be 74 and 84dB, respectively, and those at 20GHz were 84 and 96dB, respectively.Superconducting modulator circuits with a 1-to-4 demultiplexer and dc-biased latching-type output drivers were designed and fabricated using Nb circuit technology. The modulator circuits showed clear noise shaping characteristics in the output spectra. The SNR and SFDR for the signal bandwidth of 10MHz at fs of 10GHz were obtained to be 64 and 74dB, respectively.

An enhanced first-order sigma-delta modulator with a controllable signal-to-noise ratio

This paper presents an enhanced first-order sigma-delta modulator. The proposed modulator, derived using the Al-Alaoui operator, outperforms the conventional modulator. A comparison is drawn showing that the conventional sigma-delta modulator is a special case of the enhanced sigma-delta modulator. The paper includes an analytical derivation as well as extensive simulations revealing the superiority of the proposed modulator reaching optimal performance

Driven interval shift dynamics in sigma-delta modulators and phase-locked loops

In this paper, we show how consideration of the first-order sigma-delta (/spl Sigma//spl Delta/) modulator with sampled periodic input motivates study of the maps known mathematically as driven interval shifts. We derive new results concerning the behavior of these maps, and apply these results to provide new insight into the behavior of /spl Sigma//spl Delta/ modulators and phase-locked loops. We will see that viewing these systems through the mechanism of the driven interval shift allows us to identify common features in their behavior.

Modeling of Superconducting First- and Second-Order Low-Pass Sigma-Delta Modulators

Here we present our studies of first- and second-order superconducting low-pass sigma-delta modulators with the filtering function realized using an RL-circuit. These modulators have been simulated for different circuit parameters using device level simulations. A linear discrete time model of the first-order modulator has been done. Simulations of the first-order sigma-delta modulator operating at an oversampling ratio of 128 and a bandwidth of 60 MHz give a maximum SNR of 70 dB using a resistance of only 1 m/spl Omega/. The SNR dependence on the parameters of the RL-filter is well predicted by the linear model. Some circuit parameters give however rise to harmonic distortions which can not be predicted by the simple linear model. Under the same conditions, the performance of second-order sigma-delta modulators was found to have a maximum SNR of only 82 dB. We conclude that the estimated upper bound on SNR for superconducting RL-filtered low-pass sigma-delta modulators, is for physical realizable circuits not high enough to give an advantage over other techniques.

IEC class 0.5 electronic watt–hour meter implemented with first-order sigma–delta converters

This paper presents a design of a precise electronic watt–hour meter implemented with first-order sigma–delta analog-to-digital converters. An efficient digital signal-processing circuit is introduced into the design where the whole signal processing is performed directly on an oversampled signal, eliminating the necessity for a decimation filter. It is shown that Gaussian noise, added to the input signal of sigma–delta modulators, decorrelates quantization error of first-order sigma–delta modulators and thus substantially reduces measurement error at low-signal amplitudes. The effect of added noise is analyzed by extensive behavioral simulations for various input signal amplitudes and for various input noise levels. The results show that IEC accuracy class 0.5 can be achieved with first-order sigma–delta converters and digital signal processing in the sigma–delta domain.