First-in First-out Queue Research Articles

Fast and Portable Concurrent FIFO Queues With Deterministic Memory Reclamation

In this article we present an algorithm for a high performance, unbounded, portable, multi-producer/multi-consumer, lock-free FIFO (first-in first-out) queue. Aside from its competitive performance on current hardware, it is further characterized by its integrated memory reclamation mechanism, which is able to reliably and deterministically de-allocate nodes as soon as the final operation with a reference has concluded, similar to reference counting. This differentiates our approach from most other lock-free data structures, which usually require external (generic) memory reclamation or garbage collection mechanisms such as hazard pointers. Our deterministic memory reclamation mechanism completely prevents the build up of memory awaiting reclamation and is hence very memory efficient, yet it does not introduce any substantial performance overhead. By utilizing concrete knowledge about the internal structure and access patterns of our queue, we are able to construct and constrain the reclamation mechanism in such a way that keeps the overhead for memory management almost entirely out of the common fast path. The presented algorithm is portable to all modern 64-bit processor architectures, as it only relies on the commonly available and lock-free atomic synchronization primitives compare-and-swap and fetch-and-add.

MODEL SISTEM ANTRIAN PADA PELAYANAN RESTORAN CEPAT SAJI (Studi Kasus di KFC Gajah Mada Kabupaten Jember)

KFC is one of the fast food restaurants in the Jember Regency which is never deserted of visitors, especially that on Gajah Mada Street. The purposes of this study were to determine the characteristics of the queuing system, analyze the queuing applied at KFC, formulate recommendations for improving the queuing system to reduce queuing, and minimize costs. The Data analysis was performed to compare manual calculations and simulation methods using ARENA 14.0. The characteristics of the current queue at KFC are random and unlimited arrival patterns, FIFO (first in first out) queue discipline, and the design of the single phase multi channel queuing system. The queuing distribution used for arrival and service time was the exponential distribution. The queuing model notation at the M/M/2 cashier: FIFO/∞/∞. The recommended queuing model that can be applied was to add 1 cashier to 3 cashiers at a cost of Rp 150,560 from the scenario made. The performance variable in the scenario becomes less than the initial condition, which was ρ cashier becomes 188%, total Wq about 0.92 minutes, and Lq about 2 people. Adding these facilities changes the queuing model notation to (M/M/3: FIFO/∞/∞).
 Keywords: ARENA, FIFO queuing discipline KFC Jember, queuing system

Two‐port–two‐port SI between RS485 and Ethernet with an FIFO queue for efficient PC‐to‐PC communication

This study proposes a two-port Ethernet and two-port RS485 network serial interface (SI) for packet transformation and data transmission for computer-to-computer communication. The proposed SI, which is composed of an RS485 module, an Ethernet module, a transmitter manager, a receiver manager, and the manager first-in–first-out (FIFO) queue, not only increases the data transmission rate but also guarantees correct communication between two Ethernet modules and two RS485 modules. An application-specific integrated circuit is proposed to increase the operation frequency of the two-port–two-port SI. Furthermore, the large FIFO size enables the transmission of the maximum Ethernet packet length of 88 B and allows the latency of 51 clocks to be overcome. The measurement results indicate that the operating frequency, baud rate, data transfer rate, power consumption, processing delay, gate count, and chip size are 125 MHz, 115,200 Hz, 1 Gbps, 137 mW, 139.31 µs, 162,300, and 1.27 × 1.27 mm2, respectively, at a power supply of 1.8 V and total FIFO queue of 10 kB. The error between the theoretical throughput (7.342 Mbps) and the measured throughput (7.5067 Mbps) was ∼2.24%.

USB Transceiver With a Serial Interface Engine and FIFO Queue for Efficient FPGA-to-FPGA Communication

This paper presents a universal serial bus (USB) transceiver with a serial interface engine (SIE) and an asynchronous first-in first-out (FIFO) queue for packet transformation and data transmission in field-programmable gate array (FPGA)-to-FPGA communication. The SIE block receives the data to be transmitted from the central processing unit of a PC and transfers those data to the universal transceiver macrocell interface, which handles data serialization and deserialization, bit stuffing, clock recovery, and clock synchronization. An asynchronous FIFO queue of 2 kilobits is designed to guarantee correct communication between two FPGA development boards. A parallel-in serial-out block converts parallel input data into serial data. A product identification (PID) check block determines whether the serial data are in the USB packet format. The cyclic redundancy check (CRC) checksums, namely CRC5 and CRC16, are presented with data check statements. After passing through the NRZI decoder, bit-unstuffing, PID check, and CRC16 blocks, the received serial data are converted into parallel output data by using a serial-in parallel-out block. The FPGA-to-FPGA communication design operates correctly. An application-specific integrated circuit (ASIC) of the USB transceiver is implemented using TSMC 0.18-μm CMOS technology. The gate counts, power consumption, operating frequency, and chip area of the ASIC are 14,547, 2.6742 mW, 50 MHz, and 0.7 × 0.67 mm 2 , respectively, at a supply voltage of 1.8 V and total pin number of 38.

Optimal Policies for Status Update Generation in an IoT Device With Heterogeneous Traffic

A large body of applications that involve monitoring, decision making, and forecasting require timely status updates for their efficient operation. Age of Information (AoI) is a newly proposed metric that effectively captures this requirement. Recent research on the subject has derived AoI optimal policies for the generation of status updates and AoI optimal packet queueing disciplines. Unlike previous research, we focus on low-end devices that typically support monitoring applications in the context of the Internet of Things. We acknowledge that these devices host a diverse set of applications some of which are AoI sensitive while others are not. Furthermore, due to their limited computational resources, they typically utilize a simple first-in–first-out (FIFO) queueing discipline. We consider the problem of optimally controlling the status update generation process for a system with a source–destination pair that communicates via a wireless link, whereby the source node is composed of a FIFO queue and serves two applications, one that is AoI sensitive and one that is not. We formulate this problem as a dynamic programming problem and utilize the framework of Markov decision processes to derive the optimal policy for the generation of status update packets. Due to the lack of comparable methods in the literature, we compare the derived optimal policies against baseline policies such as the zero-wait policy. Results indicate that the baseline policy fails to capture the complex system dynamics that determine the relationship between the frequency of status update generation and the resulting queueing delay and thus perform poorly. To the best of our knowledge, the derived optimal policy does not exhibit a simple structure; thus, we utilized the baseline policies, whose operation is intuitive, to gain insight into the inner workings of the optimal policy.

Racetrack Queues for Extremely Low-Energy FIFOs

Networks-on-chip (NoCs) have become a leading energy consumer in modern multicore processors, with a considerable portion of this energy originating from the large number of virtual channel first-in–first-out (FIFO) buffers. Given this motivation, we propose control schemes that leverage the “shift-register” nature of spintronic domain-wall memory (DWM) to create extremely low-energy FIFO queues. In order to test these queues in the most relevant application context, replacing conventional memory buffers for NoCs, we perform design-space analysis over the different schemes in a network context and then analyze the best schemes with benchmark traffic. Our results indicate that the best shift-based buffer utilizes a dual-nanowire approach to ensure that reads and writes can be more effectively aligned with access ports for simultaneous access in the same cycle. Our approach provides a $2.93\times $ speedup over a DWM buffer using a traditional FIFO memory control scheme with a 23.4% savings in energy. The resulting approach achieves a 39% reduction in energy-delay product compared to SRAM and a 24% reduction in energy-delay product versus spin-transfer torque magnetic memories.

Efficient priority queueing routing strategy on networks of mobile agents

As a consequence of their practical implications for communications networks, traffic dynamics on complex networks have recently captivated researchers. Previous routing strategies for improving transport efficiency have paid little attention to the orders in which the packets should be forwarded, just simply used first-in–first-out queue discipline. Here, we apply a priority queuing discipline and propose a shortest-distance-first routing strategy on networks of mobile agents. Numerical experiments reveal that the proposed scheme remarkably improves both the network throughput and the packet arrival rate and reduces both the average traveling time and the rate of waiting time to traveling time. Moreover, we find that the network capacity increases with an increase in both the communication radius and the number of agents. Our work may be helpful for the design of routing strategies on networks of mobile agents.

The curse of the first-in–first-out queue discipline

We consider a game in which a large number of identical agents choose when to queue up at a single server after it opens. Agents are impatient for service and also incur a cost proportional to time spent in the queue. We show that the first-in–first-out queue discipline and the last-in–first-out queue discipline both lead to a unique equilibrium arrival distribution. However, among all work-conserving queue disciplines, the first-in–first-out performs the worst in terms of equilibrium utility and welfare, while the last-in–first-out performs the best.

An integrated algorithm to evaluate flow direction and flow accumulation in flat regions of hydrologically corrected DEMs

In order to conduct an accurate hydrological analysis of a watershed, certain conditions need to be understood. Flow direction and flow accumulation are important watershed characteristics that need to be determined before an analysis can be made. Other important characteristics which can be gleaned from analysing the digital elevation model (DEM) of a watershed include channel networks, stream lengths and watershed boundaries. Determining flow direction and flow accumulation is usually carried out in separate steps. Flat regions are types of terrain in raster DEMs without local elevation gradients. Evaluating flow direction and flow accumulation in flat regions using DEMs is a well-known problem in watershed analysis because of the occurrence of problematic parallel flow lines. Calculations also tend to be time-consuming. We have developed an efficient and comprehensive integrated approach to assign flow directions and flow accumulation in flat regions. This approach uses values for non-flat flow accumulation and a maze algorithm with a weight value (MW method) to determine several things: a main flow line through the flat area to the local outlet, an octree tree, and first-in first-out queue structures to calculate flow accumulation. The MW method can be applied to hydrologically corrected DEMs and a single flow path can be provided to resolve all flat areas. To investigate the influence on the topological properties of the channel networks, we used this integrated algorithm to extract three sets of flow accumulation areas from existing DEMs. Using this new integrated method was faster than using the two existing methods and produced continuous channel networks without the occurrence of problematic parallel flow lines.

Extending Worst Case Response-Time Analysis for Mixed Messages in Controller Area Network With Priority and FIFO Queues

The existing worst case response-time analysis for controller area network (CAN) with nodes implementing priority and First In First Out (FIFO) queues does not support mixed messages. It assumes that a message is queued for transmission either periodically or sporadically. However, a message can also be queued both periodically and sporadically using mixed transmission mode implemented by several higher level protocols for CAN that are used in the automotive industry. We extend the existing analysis for CAN to support any higher level protocol for CAN that uses periodic, sporadic, and mixed transmission of messages in the systems where some nodes implement priority queues, whereas others implement FIFO queues. In order to provide a proof of concept, we implement the extended analysis in a free tool, conduct an automotive-application case study, and perform comparative evaluation of the extended analysis with the existing analysis.

Symbolic Supervisory Control of Distributed Systems With Communications

We consider the control of distributed systems composed of subsystems communicating asynchronously; the aim is to build local controllers that restrict the behavior of a distributed system in order to satisfy a global state avoidance property. We model distributed systems as communicating finite state machines with reliable unbounded first in, first out (FIFO) queues between subsystems. Local controllers can only observe the behavior of their proper subsystem and do not see the queue contents. To refine their control policy, controllers can use the FIFO queues to communicate by piggy-backing extra information (some timestamps and their state estimates) to the messages sent by the subsystems. We provide an algorithm that computes, for each local subsystem (and thus for each controller), during the execution of the system, an estimate of the current global state of the distributed system. We then define a synthesis algorithm to compute local controllers. Our method relies on the computation of (co-)reachable states. Since the reachability problem is undecidable in our model, we use abstract interpretation techniques to obtain overapproximations of (co-)reachable states. An implementation of our algorithms provides an empirical evaluation of our method.

Modelling and Simulation of Adaptive Buffer Management Mechanism Using Nested Autoregressive Process-Based Mpeg-Encoded Traffic Model

High speed networks provide real-time variable bit rate (VBR) service with diversified traffic flow characteristics and quality requirements. The VBR traffic has stringent delay and packet loss requirements. The burstiness of the correlated traffic makes dynamic management highly desirable to satisfy the Quality of Service (QoS) requirements. Buffer management in queueing systems plays important role towards effective control of QoS for various types of applications. In this paper, ADaptive Partial Buffer Sharing (ADPBS) scheme for priority queueing system is proposed and analyzed. The input to the queue has been taken using auto-regressive (AR) process of order 2 for MPEG-encoded VBR video traffic. The results of simulations indicate that dynamically controlled threshold in ADPBS contributes in reducing the packet loss of different priority classes as compared with static partial buffer sharing queue and first-in first-out queue based on threshold control parameters and the traffic type.

MODELLING AND SIMULATION OF ADAPTIVE BUFFER MANAGEMENT MECHANISM USING NESTED AUTOREGRESSIVE PROCESS-BASED MPEG-ENCODED TRAFFIC MODEL

AbstractHigh speed networks provide real-time variable bit rate (VBR) service with diversified traffic flow characteristics and quality requirements. The VBR traffic has stringent delay and packet loss requirements. The burstiness of the correlated traffic makes dynamic management highly desirable to satisfy the Quality of Service (QoS) requirements. Buffer management in queueing systems plays important role towards effective control of QoS for various types of applications. In this paper, ADaptive Partial Buffer Sharing (ADPBS) scheme for priority queueing system is proposed and analyzed. The input to the queue has been taken using auto-regressive (AR) process of order 2 for MPEG-encoded VBR video traffic. The results of simulations indicate that dynamically controlled threshold in ADPBS contributes in reducing the packet loss of different priority classes as compared with static partial buffer sharing queue and first-in first-out queue based on threshold control parameters and the traffic type.

Recursive Constructions of Parallel FIFO and LIFO Queues With Switched Delay Lines

One of the most popular approaches for the constructions of optical buffers needed for optical packet switching is to use switched delay lines (SDL). Recent advances in the literature have shown that there exist systematic SDL construction theories for various types of optical buffers, including first-in first-out (FIFO) multiplexers, FIFO queues, priority queues, linear compressors, nonovertaking delay lines, and flexible delay lines. As parallel FIFO queues with a shared buffer are widely used in many switch architectures, e.g., input-buffered switches and load-balanced Birkhoff-von Neumann switches, in this paper we propose a new SDL construction for such queues. The key idea of our construction for parallel FIFO queues with a shared buffer is two-level caching, where we construct a dual-port random request queue in the upper level (as a high switching speed storage device) and a system of scaled parallel FIFO queues with a shared buffer in the lower level (as a low switching speed storage device). By determining appropriate dumping thresholds and retrieving thresholds, we prove that the two-level cache can be operated as a system of parallel FIFO queues with a shared buffer. Moreover, such a two-level construction can be recursively expanded to an n-level construction, where we show that the number of 2times2 switches needed to construct a system of N parallel FIFO queues with a shared buffer B is O((NlogN)log(B/(NlogN))), for NGt1. For the case with N=1, i.e., a single FIFO queue with buffer B, the number of 2times2 switches needed is O(logB). This is of the same order as that previously obtained by Chang We also show that our two-level recursive construction can be extended to construct a system of N parallel last-in first-out (LIFO) queues with a shared buffer by using the same number of 2times2 switches, i.e., O((NlogN)log(B/(NlogN))), for NGt1 and O(logB) for N=1. Finally, we show that a great advantage of our construction is its fault tolerant capability. The reliability of our construction can be increased by simply adding extra optical memory cells (the basic elements in our construction) in each level so that our construction still works even when some of the optical memory cells do not function properly

Distributed Neural Networks for Quality of Service Estimation in Communication Networks

We study an original scheme based on distributed feedforward neural networks, aimed at modelling several queueing systems in cascade fed with bursty traffic. For each queueing system, a neural network is trained to anticipate the average number of waiting packets, the packet loss rate and the coefficient of variation of the packet inter-departure time, given the mean rate, the peak rate and the coefficient of variation of the packet inter-arrival time. The latter serves for the calculation of the coefficient of variation of the cell inter-arrival time of the aggregated traffic which is fed as input to the next neural network along the path. The potential of this method is successfully illustrated on several single server FIFO (First In, First Out) queues and on small queueing networks made up from a combination of queues in tandem and in parallel fed by a superposition of ideal sources. Our long-term goal is the design of preventive control strategy in a multiservice communication network.

Elastic calls in an integrated services network: the greater the call size variability the better the QoS

We study a telecommunications network integrating stream calls and elastic calls that share a given number of available traffic channels. The prioritised speech calls are handled as in a traditional Erlang loss model, while the delay-tolerant elastic calls are served with the remaining (varying) service capacity according to a processor sharing (PS) discipline. The remarkable observation is presented and analytically supported that the expected elastic call holding time is decreasing in the variability of the elastic call size distribution. This phenomenon is demonstrated for both Weibull and Pareto elastic call size distributions. Since the reverse effect is known to hold if elastic calls are served in a first-in first-out (FIFO) manner, an extended model is considered which limits the number of service positions in the elastic calls’ PS queue and holds excessive calls into a feeding FIFO queue. The impact of the elastic call size variability is demonstrated to depend on the number of service positions in the PS queue, as this determines whether the ‘PS’ or the (reverse) ‘FIFO effect’ is dominant. As a consequence of the principal result, network planning guidelines or admission control schemes that are developed based on deterministic or lightly variable elastic call sizes are likely to be conservative and inefficient, given the commonly acknowledged property of e.g. WWW documents to be heavy-tailed. Application areas of the models and results include fixed TCP/IP or ATM networks and mobile cellular GSM/GPRS and UMTS networks.

Multidimensional synchronous dataflow

Signal flow graphs with dataflow semantics have been used in signal processing system simulation, algorithm development, and real-time system design. Dataflow semantics implicitly expose function parallelism by imposing only a partial ordering constraint on the execution of functions. One particular form of dataflow called synchronous dataflow (SDF) has been quite popular in programming environments for digital signal processing (DSP) since it has strong formal properties and is ideally suited for expressing multirate DSP algorithms. However, SDF and other dataflow models use first-in first-out (FIFO) queues on the communication channels and are thus ideally suited only for one-dimensional (1-D) signal processing algorithms. While multidimensional systems can also be expressed by collapsing arrays into 1-D streams, such modeling is often awkward and can obscure potential data parallelism that might be present. SDF can be generalized to multiple dimensions; this model is called multidimensional synchronous dataflow (MDSDF). This paper presents MDSDF and shows how MDSDF can be efficiently used to model a variety of multidimensional DSP systems, as well as other types of systems that are not modeled elegantly in SDF. However, MDSDF generalizes the FIFO queues used in SDF to arrays and, thus, is capable only of expressing systems sampled on rectangular lattices. This paper also presents a generalization of MDSDF that is capable of handling arbitrary sampling lattices and lattice-changing operations such as nonrectangular decimation and interpolation. An example of a practical system is given to show the usefulness of this model. The key challenge in generalizing the MDSDF model is preserving static schedulability, which eliminates the overhead associated with dynamic scheduling, and preserving a model where data parallelism, as well as functional parallelism, is fully explicit.

ANALYZING THE RECEIVING OPERATION OF DIFFERENT GRAIN TYPES IN A SINGLE–PIT COUNTRY ELEVATOR

With the rise of valueadded grains and oilseeds, many elevators need to segregate their incoming products intobatches of different enduse quality (for example, high oil corn, genetically modified soybeans, high protein wheat), but oftenthey are not designed to handle this task efficiently. The primary challenge is to segregate multiple grain streams during thereceiving operation without increasing waiting times for all customers.This study utilized a system simulation model to investigate how queue management could help to improve the performanceof a country elevator receiving multiple grain streams with a single unloading pit. In order to maintain the speed of theunloading operation, two queuing methods were investigated: the segregated BATCH versus the traditional FIFO (firstin,firstout) queue service method. A discrete event system simulation model was developed and validated utilizing datacollected at a country elevator facility in Indiana. The simulation results showed that the BATCH queue management strategyreduced average waiting times per customer by up to 27% compared to the traditional FIFO queue management strategy whenthe daily grain receipt was near the maximum receiving capacity of the facility. For receiving rates below 72% capacity, thetraditional FIFO service had shorter average waiting times per customer.

A note on the conservation law for queues with batch arrivals

The conservation law formula for work-conserving queues with batch arrivals is derived for when the arrival instants of customers are assumed to constitute an arrivals see time averages (ASTA) process. The derivation is based on the analysis of the corresponding first-in first-out (FIFO) multiclass queue and its steady state. Hence, the mean work load in the queue at an arbitrary time instant can be equated with the mean time that an arbitrary customer has to wait in the FIFO queue. >

Synthesizing a protocol converter from executable protocol traces

Communicating finite state machines (CFSM's) with FIFO (first in, first out) queues are used to model a protocol converter. A protocol conversion algorithm is developed and presented for the CSFM model of the protocols A and B. A converter H for protocols A=(A/sub 0/, A/sub 1/) and B=(B/sub 0/, B/sub 1/) is viewed as a black box such that H is between sender A/sub 0/ and receiver B/sub 1/. This gives a resulting protocol X=(A/sub 0/, H, B/sub 1/). The conversion algorithm requires a specification of the message relationships between the messages of protocols A and B. It is assumed that protocols A and B have the required progress properties. The algorithm includes a search for related messages from the two protocols in an FIFO from a composite space formed by a Cartesian cross-product of state spaces A/sub 1/ and B/sub 0/. The search produces finite-length traces which are combined to form a state machine H, which is examined for freedom from unspecified receptions, deadlocks, and livelocks. A protocol conversion example demonstrates the applicability of the algorithm.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>