Firmware Solutions Research Articles

Developing Two-Armed Robot Assistant: Selecting Lines of Research

Background/Objectives: The objective of this study is to select the lines of research for implementing constructive and firmware solutions to create universal robot that would perform different simple tasks. Methods: Such technical solutions will be used for further development of different types of robots of either anthropomorphic or of any other random configuration designed for performing a wide spectrum of tasks in industrial, social or domestic environments. Findings: The study presents the results of the analysis of information sources and patent research studies on the areas as follows: principles of building hardware and software complexes for two-armed assistant robots that would partially replace manual labor in remote object handling operations; algorithms for controlling kinematic joints of the manipulator that implement the principles of inverse kinematics and dynamics to ensure safe working environment for man in the process of human-robot collaboration; methods of coordinated control over two manipulators. Applications/Improvements: The results of the study can be applied to constructive and firmware solutions in the process of creating a universal robot to replace manual labor in remote autonomous operations.

Energy Consumption Estimation for Embedded Applications

Energy consumption, indeed, represents one of the essential properties of embedded applications, especially for those devices whose autonomy depends on battery life. The lack of accurate and suitable methodology for energy consumption estimation for embedded applications based on ultra-low power heterogeneous multicore DSP platforms inspired a solution that will be presented in this paper. The solution has been developed as a plugin for the Eclipse based MIDE (Multicore Integrated Development Environment), in order to facilitate production of energy efficient firmware solutions. Evaluation of energy loss has been calculated using instruction-level power analysis, virtual platform, debug information, and diverse input loads. The primary goal was to obtain a precise model of energy consumption that will establish a direct link between program solutions and the amount of energy required for their execution, whilst processing different input loads. Estimation has been validated against empirical data, measured on a real DSP platform. Results show that very high accuracy has been reached.DOI: http://dx.doi.org/10.5755/j01.eie.22.3.15313

Versatile prototyping platform for Data Processing Boards for CBM experiment

The CBM experiment is one of the experiments prepared at the FAIR Facility in Darmstadt. The Data Processing Boards (DPB) are an important component of the CBM readout chain. Before the final, production versions of DPB may be designed, it is important to create a prototyping platform, to test and select appropriate hardware and firmware solutions. The Kintex based AMC FMC Carrier (AFCK) board is a versatile and open solution fulfilling those requirements, offering configurable high-speed (up to 10 Gbps) connectivity. The paper describes the AFCK hardware, the firmware architecture, and the IP cores developed for different DPB prototyping tasks. Due to its versatility and openness the AFCK may be reused in other experiments.

Developing Two-Armed Robot Assistant: Intelligent Tutoring Skills Based System

Background/Objectives: The objective of this study is to develop constructive and firmware solutions to create universal robot that would perform different simple tasks and replace human labor in remote autonomous operations. Methods: Specific features of the suggested learning method are represented by the possibilities to copy and exchange skills between different robots including those that possess different kinematic schemes. This becomes possible due to the adaptive control over the manipulator links in line with the current configuration of the effective area. Findings: The study suggests an approach to controlling robots as they perform operations under different conditions including those that are not predetermined by the working area and in cases with obstacles based on earlier obtained knowledge (skills) and according to the universal model of control over performing one particular acquired practice (complex operation with objects) in undetermined environment as a combination of elementary actions performed in real-time mode revealing the capability of adapting to the changing conditions of the environment. Applications/Improvements: The results of the study can be applied to constructive, hardware and software solutions in the process of developing a universal robot to replace manual labor in remote autonomous operations.

A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run-2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources. Together with auxiliary memories, all these components form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for high speed input and output fiberoptic links and TTC allowed the full system of 320 input links from the 32 chambers to be processed by 6 COBs in one ATCA shelf. The full system was installed in September 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning for LHC Run 2.

A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

The ATLAS muon Cathode Strip Chamber (CSC) back-end readout system has been upgraded during the LHC 2013–2015 shutdown to be able to handle the higher Level-1 trigger rate of 100kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip Xilinx Zynq series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the Zynq for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf through software waveform feature extraction to output 32 S-links. The full system was installed in Sept. 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning towards LHC Run 2.

Cost-Effective FPGA Instrument for Harmonic and Interharmonic Monitoring

The need of large-scale monitoring of power quality (PQ) in electrical power systems require the design of reliable and cost-effective measurement instruments. In this framework, Field Programmable Gate Array (FPGA) architectures seem to offer valid solutions since they allow powerful measurement algorithms to be implemented on low-cost hardware with reconfigurable firmware. This paper proposes a FPGA-based measurement instrument for harmonic and interharmonic monitoring in compliance with the most important PQ standards. Key feature of the proposed instrument is the very low requirements of hardware and firmware FPGA resources, thus making it suitable for applications that require cost-effective measurements. The proposed instrument shows performance comparable with one of the powerful and more expensive measurement solutions available on the market. In particular, despite the absence of a sampling frequency synchronization system, the proposed instrument proves to be compliant with IEC 61000-4-30, even in the presence of huge frequency deviations. After a description of the proposed hardware and firmware solutions, the experimental characterization of the proposed instrument in emulated and real environments is reported.

A FPGA-based instrument for power measurement in DVB-T systems

This paper deals with the implementation of an innovative measurement instrument for power measurement in Digital Video Broadcasting Terrestrial (DVB-T) systems.In previous researches the authors have designed and tuned the measurement method. It is based on a digital signal processing section, which properly estimates the power spectrum density (PSD) of the input DVB-T signal. The peculiarities of the selected measurement algorithm have suggested the development of the instrument on a suitable FPGA platform.In this paper the hardware and the software architectures of an innovative instrument implementing the cited method are proposed. It is characterized by high transportability and exhibits metrological performance comparable with that peculiar to state-of-the-art. In particular, both the firmware solutions and optimizations, proposed to limit the resource demanding and making use of the massive parallelism offered by the FPGA architecture, are described in detail.A number of experimental tests carried out on actual DVB-T signals are also presented, whose results show the good metrological performance of the realized instrument. All measurement results concur with those provided by competitive commercial solutions.