Finite State Machine Specification Research Articles

Implementation of FSM Based Chat-Bots in a Graphical Designer

Finite state machine (FSM) is a powerful tool to model object behavior. Using FSM and its extensions to model program behavior followed by the automatic generation of executable code is the approach encouraged by the model-driven development (MDD) – a software development methodology based on the concepts of model and model transformation.In this paper, a brief overview of FSM-based common methods to model and develop software programs of any nature is given. These methods include David Harel’s statecharts, UML State Machines, Virtual Finite State Machine, etc. Examples of all types of software systems (transformational, interactive, reactive) implemented using FSM are cited.Chat-bots as an example of an interactive software system are considered: concept, classification methods, implementation techniques. A graphical designer of rule-based chat-bots to be integrated in the messenger Telegram is developed and implemented. In this designer, chat-bot behavior is modeled using FSM.Formal method to model a rule-based chat-bot using FSM is provided. The FSM concept is extended by disabled transitions to save history of transition changes made during the FSM design process. A brief overview of code generation methods from FSM specification is done; advantages and disadvantages of the most popular approaches are considered. Dynamic approach to generate code by FSM specification saved in DB is proposed. To implement this approach, document MongoDB and in-memory key-value Redis DB are used; FSM is kept as a JSON-document. This approach is efficient in flexibility, speed and memory needs.Architecture diagram of developed chat-bot graphical designer is given. It has the microservice architecture. The FSM model-to-code transformation is carried out by the bot-execution service written using compiled language Go. Other services include the front-end (UI for end-user, CRUD API for chat-bot) and the bot-management (synchronization of document and key-value databases) services.

Assessing test suites of extended finite state machines against model‐ and code‐based faults

SummaryTests can be derived from extended finite state machine (EFSM) specifications considering the coverage of single‐transfer faults, all transitions using a transition tour, all‐uses, edge‐pair, and prime path with side trip. We provide novel empirical assessments of the effectiveness of these test suites. The first assessment determines for each pair of test suites if there is a difference between the pair in covering EFSM faults of six EFSM specifications. If the difference is found significant, we determine which test suite outperforms the other. The second assessment is similar to the first; yet, it is carried out against code faults of 12 Java implementations of the specifications. Besides, two assessments are provided to determine whether test suites have better coverage of certain classes of EFSM (or code) faults than others. The evaluation uses proper data transformation of mutation scores and p‐value adjustments for controlling Type I error due to multiple tests. Furthermore, we show that subsuming mutants have an impact on mutation scores of both EFSM and code faults; and accordingly, we use a score that removes them in order not to invalidate the obtained results. The assessments show that all‐uses tests were outperformed by all other tests; transition tours outperformed both edge‐pair and prime path with side trips; and single‐transfer fault tests outperformed all other test suites. Similar results are obtained over the considered EFSM and code fault domains, and there were no significant differences between the test suites coverage of different classes of EFSM and code faults.

Test generation algorithm for the All-Transition-State criteria of Finite State Machines

In the current article a novel test generation algorithm is presented for deterministic finite state machine specifications based on the recently introduced All-Transition-State criteria. The size of the resulting test suite and the time required for test suite generation are investigated through analytical and practical analyses and are also compared to the Transition Tour, Harmonized State Identifiers and random walk test generation methods. The fault detection capabilities of the different approaches are also investigated with simulations applying randomly injected transfer faults.

FSM quasi-equivalence testing via reduction and observing absences

There has been significant interest in automatically generating test cases from a non-deterministic finite state machine (FSM). Most approaches check that the behaviours of the system under test (SUT) are allowed by the specification FSM; they therefore test for reduction . However, sometimes one wants all of the behaviours, and so features, of the specification to be implemented and then one is testing for equivalence . In this paper we first note that in order to test for equivalence one must effectively be able to observe the SUT not being able to produce an output y in response to an input x after trace σ ¯ ; we model this as the absence of an output. We prove that the problem of testing for equivalence to FSM M can be mapped to testing for reduction to an FSM R ( M ) that extends M with absences. Thus, one can use techniques developed for testing for reduction when testing for equivalence. We then consider the case where the specification is partial, generalising the result to quasi-equivalence. These results are proved for observable specifications and so we also show how a partial FSM can be mapped to an observable partial FSM from which we can test. • Generalises quasi-reduction and quasi-equivalence to non-observable FSMs. • Any technique, for testing for reduction, can be used for testing for quasi-equivalence. • A partial FSM can be mapped to an observable partial FSM.

Влияние частичности и адаптивности на сложность задачи идентификации состояний автомата

State identification is a long standing problem in the area of Finite State Machine (FSM) based modeling and testing of discrete event systems. For the identification of the current state of the system, so-called homing and synchronizing experiments with FSMs are used whereas for the initial state identification one can perform a distinguishing experiment. The homing, synchronizing, and distinguishing experiments are known as “gedanken” experiments, and the sequences for these experiments can be derived for deterministic and nondeterministic, partial and complete specification FSMs that are used to formally represent the required behavior of systems under investigation. The problems of checking the existence and derivation of homing, synchronizing, and distinguishing sequences are known to become harder as a specification FSM turns to be nondeterministic and partial. It is also known that in some cases the complexity can be reduced through a ‘switch’ from preset to adaptive experiment derivation. In this paper, we study how the partiality and adaptivity affect the complexity of checking the existence of homing/synchronizing/distinguishing sequences for deterministic and nondeterministic FSMs and visualize the complexity issues via appropriate figures. We also mention that the existing solutions to state identification problems are widely used for verification and testing of finite state transition systems.

FORTIFIER: a FORmal disTrIbuted Framework to Improve the dEtection of thReatening objects in baggage

ABSTRACTCurrently, security breaches in public places like airports and official buildings are a major concern by both governmental and corporative organizations. In these situations, X-ray devices must scan a vast amount of baggage in a short time frame. Hence, deploying scanners that automatize the task of detecting suspicious artefacts becomes of vital importance to prevent from threats. In this paper we present FORTIFIER, a formal distributed framework designed to detect suspicious artefacts. This approach consists in the integration of several image detection algorithms executed in a distributed environment, which are aimed to detect a wide spectrum of weapons like guns, knifes and bombs. The main core of our proposed framework for recognizing suspicious artefacts is divided in different phases, where each one is modelled with a specific finite state machine (FSM). Several FSMs are combined to detect different artefacts. We also present a case of study where some performance experiments are carried out for analysing the scalability of FORTIFIER. Initially, FORTIFIER is deployed in a single cloud environment. Once the main features that have a significant impact on the overall system performance are analysed, our proposed framework is deployed in a multi-cloud environment.

Parallel algorithms for reducing derivation time of distinguishing experiments for nondeterministic finite state machines

Many approaches have been proposed for deriving tests from finite state machine (FSM) specifications with respect to some established coverage criteria. A fundamental core problem in FSM-based testing relates to the derivation of input sequences that can distinguish states of an FSM specification, aka distinguishing sequences. A major effort in the construction of these sequences is based on the derivation of a successors search-tree labeled by sets of pairs of states of the given machine. We aim at reducing the time associated with such constructions through the use of state-of-the-art parallel technologies. Namely, we propose a parallel algorithm that we implement and evaluate on multicore CPUs and on many-core GPUs. We evaluate two alternative GPU implementations that use the CUDA and Thrust software platforms and a network of workstations based solution. The latter sports a workload partitioning based on Divisible Load Theory. A rigorous set of experiments highlights the differences of the proposed implementations in terms of execution time and speedup.

Heuristics for deriving distinguishing experiments of nondeterministic finite state machines

Derivation of input sequences for distinguishing states of a finite state machine (FSM) specification is well studied in the context of FSM-based functional testing. We present three heuristics for the derivation of distinguishing sequences for nondeterministic FSM specifications. The first is based on a cost function that guides the derivation process and the second is a genetic algorithm that evolves a population of individuals of possible solutions (or input sequences) using a fitness function and a crossover operator specifically tailored for the considered problem. The third heuristic is a mutation based algorithm that considers a randomly generated input sequence as a candidate solution, and if the candidate is not a distinguishing sequence, then the algorithm tries to find a solution by appropriately mutating the considered candidate. Experiments are conducted to assess the performance of the considered algorithms with respect to execution time, virtual memory consumption, and quality (length) of obtained sequences. Experiments are conducted using randomly generated machines with a various number of states, inputs, outputs, and degrees of non-determinism. Further, we assess the impact of varying the number of states, inputs, outputs, and degree of non-determinism.

Designing Trusted Embedded Systems from Finite State Machines

Sequential components are crucial for a real-time embedded system as they control the system based on the system's current state and real life input. In this article, we explore the security and trust issues of sequential system design from the perspective of a finite state machine (FSM), which is the most popular model used to describe sequential systems. Specifically, we find that the traditional FSM synthesis procedure will introduce security risks and cannot guarantee trustworthiness in the implemented circuits. Indeed, we show that not only do there exist simple and effective ways to attack a sequential system, it is also possible to insert a hardware Trojan Horse into the design without introducing any significant design overhead. We then formally define the notion of trust in FSM and propose a novel approach to designing trusted circuits from the FSM specification. We demonstrate both our findings on the security threats and the effectiveness of our proposed method on Microelectronics Center of North Carolina (MCNC) sequential circuit benchmarks.

A hybrid optimization approach to conformance testing of finite automata

Unique Input–Output sequences (UIOs) are quite commonly used in conformance testing. Unfortunately finding UIOs of minimal length is an NP hard problem. This study presents a hybrid approach to generate UIOs automatically on a basis of the finite state machine (FSM) specification. The proposed hybrid approach harnesses the benefits of hill climbing (Greedy search) and heuristic algorithm. Hill climbing, which exploits domain knowledge, is capable of quickly generating good result however it may get stuck in local minimum. To overcome the problem we used a set of parameters called the seed, which allows the algorithm to generate different results for a different seed. The hill climbing generates solutions implied by the seed while the Genetic Algorithm is used as the seed generator. We compared the hybrid approach with Genetic Algorithm, Simulated Annealing, Greedy Algorithm, and Random Search. The experimental evaluation shows that the proposed hybrid approach outperforms other methods. More specifically, we showed that Genetic Algorithm and Simulated Annealing exhibit similar performance while both of them outperform Greedy Algorithm. Finally, we generalize the proposed hybrid approach to seed-driven hybrid architectures and elaborate on how it can be adopted to a broad range of optimization problems.

FSM-based testing from user defined faults adapted to incremental and mutation testing

We study the problem of deriving a test suite with guaranteed fault coverage from a given finite state machine specification with respect to some given user defined faults. We consider the case when an implementation under test can have more states than its specification while user defined faults are implemented in an arbitrary way. We show that our approach can be used for FSM-based incremental and mutation testing and correspondingly we investigate cases that can be used for reducing length of obtained test suites. In some cases, worst-case length of obtained test suite becomes polynomial. Experiments show significant gains is using our approach in comparison to testing the whole specification.

Design of reactive algorithms by solving equations over automata

The problem of solving inequalities over finite state machines (FSMs) is considered. This problem arises in the compositional approach to the design of reactive systems. The problem is formulated and solved at the level of FSM specifications in the logical language L. It is shown how to compute the maximal solution to an inequality with respect to the operation of synchronous composition of FSMs.

Exploring alternatives for transition verification

When an implementation under test (IUT) is state-based, and its expected abstract behavior is given in terms of a finite state machine (FSM), a checking sequence generated from a specification FSM and applied to an IUT for testing can provide us with high-level confidence in the correct functional behavior of our implementation. One of the issues here is to generate efficient checking sequences in terms of their lengths. As a major characteristics, a checking sequence must contain all β-sequences for transition verification. In this paper, we discuss the possibility of reducing the lengths of checking sequences by making use of the invertible transitions in the specification FSM to increase the choice of β-sequences to be considered for checking sequence generation. We present a sufficient condition for adopting alternative β-sequences and illustrate typical ways of incorporating these alternative β-sequences into existing methods for checking sequence generation to reduce the lengths. Compared to the direct use of three existing methods, our experiments show that most of the time the saving gained by adopting alternative β-sequences falls in the range of 10–40%.

Class Level Test Case Generation in Object Oriented Software Testing

Object-oriented programming consists of several different levels of abstraction, namely, the algorithmic level, class level, cluster level, and system level. In this article, we discuss a testing technique to generate test cases at class level for object-oriented programs. The formal object oriented class specification is used to develop a test model. This test model is based on finite state machine specification. The class specification and the test model is analyzed to select a set of test data for each method of the class, and finally the test cases can be generated using other testing techniques like finite-state testing or data-flow testing.

Constructing checking sequences for distributed testing

Abstract The objective of testing is to determine whether an implementation under test conforms to its specification. In distributed test architectures involving multiple remote testers, this objective can be complicated by the fact that testers may encounter coordination problems relating to controllability (synchronization) and observability during the application of tests. Based on a finite state machine (FSM) specification of the externally observable behaviour of a distributed system and a distinguishing sequence, this paper proposes a method for constructing a checking sequence where there is no potential controllability or observability problems, and where the use of external coordination message exchanges among testers is minimized. The proposed method does not assume a reliable reset feature in the implementations of the given FSM to be tested by the resulting checking sequence.

Testing from Partial Deterministic FSM Specifications

This paper addresses the problem of test generation from partially specified deterministic finite state machines (FSMs) that may have indistinguishable states and, thus, are not necessarily reduced (minimized). The known methods for checking experiments that are based on state identification are not applicable to unreduced machines. We propose the so-called state-counting approach that is directly applicable to unreduced FSMs. The approach generalizes the idea of state identification in test generation methods for deterministic machines.

Modular verification of software components in C

We present a new methodology for automatic verification of C programs against finite state machine specifications. Our approach is compositional, naturally enabling us to decompose the verification of large software systems into subproblems of manageable complexity. The decomposition reflects the modularity in the software design. We use weak simulation as the notion of conformance between the program and its specification. Following the counterexample guided abstraction refinement (CEGAR) paradigm, our tool MAGIC first extracts a finite model from C source code using predicate abstraction and theorem proving. Subsequently, weak simulation is checked via a reduction to Boolean satisfiability. MAGIC has been interfaced with several publicly available theorem provers and SAT solvers. We report experimental results with procedures from the Linux kernel, the OpenSSL toolkit, and several industrial strength benchmarks.

New approaches for passive testing using an Extended Finite State Machine specification

This paper presents two new approaches for passive testing using an Extended Finite State Machine (EFSM) specification. The state of the art of passive testing shows us that all the methods for detection of errors based on EFSMs try to match the trace to the specification. Indeed, one searches a state succession in the specification machine that is able to generate the trace observed on the implementation. Using this approach, processing is performed on the specification and the trace remains in the background since no operation is applied to it. This made us realise that focusing our efforts on the trace could be beneficial and has given as result two approaches presented in this paper that extract information from the specification and then work on the trace. Thus, they take a different direction than the previous methods. We first present an approach to test traces by using invariants resulting from the specification. We formally define these invariants and we see how to extract them. We also discuss their ability to detect errors appearing in the implementation. This approach is able to test the data flow, but not in a very satisfactory way. This is the reason for a second approach seeking to apply a set of constraints to the trace. We develop in detail its principles. Both approaches are applied to a Simple Connection Protocol ( SCP) and the results of preliminary experiments are presented.

Reconfigurable models of finite state machines and their implementation in FPGAs

This paper examines some models of finite state machines (FSMs) that can be implemented in dynamically and statically reconfigurable FPGAs. They enable circuits for the FSMs to be constructed in such a way that allows their behavior to be modified before and during run-time. This is achieved either by swapping pre-allocated areas on a chip in partially dynamically reconfigurable FPGAs, or by reloading memory-based cells in statically configured FPGAs. The initial behavioral description is presented in the form of hierarchical graph-schemes that can be formally translated to traditional FSM specifications such as state diagrams and state transition tables. The description supports modularity and a hierarchical structure, both of which are important for modifiable circuits. The results of experiments with software models that permit reconfigurable systems to be simulated and verified and with a hardware implementation of a FSM have shown that such reusable circuits require very limited FPGA resources and they can be reprogrammed in much the same way as for software development.

Automatic FSM Synthesis for Low-power Mixed Synchronous/Asynchronous Implementation

Power consumption in a synchronous FSM (Finite-State Machine) can be reduced by partitioning it into a number of coupled sub-FSMs where only the part that is involved in a state transition is clocked. Automatic synthesis of a partitioned FSM includes a partitioning algorithm and sub-FSM synthesis to an implementation architecture. In this paper, we first introduce an implementation architecture for partitioned FSMs that uses gated-clock technique for disabling idle parts of the circuits and asynchronous controllers for communication between the sub-FSMs. We then describe a new transformation procedure for the sub-FSM. The FSM synthesis flow has been automated in a prototype tool that accepts an FSM specification. The tool generates synthesizable RT-level VHDL code with identical cycle-to-cycle input/output behavior in accordance with the specification. An average power reduction of 45% has been obtained for a set standard FSM benchmarks.