Finite Impulse Response Filter Coefficients Research Articles

Implementation of a Finite Impulse Response Filter using PUFs to Avoid Trojans

In the modern era of signal processing, digital filters play an important role in real-time applications such as communication, consumer electronics, digital signal processing, audio, etc. In digital filter design, Finite Impulse Response (FIR) filters are highly preferable due to their linear phase and inherent stability. These filters benefit from being time-invariant and simple to implement with minimal computational requirements. Therefore, the hardware security of FIR filters is essential for good performance and reliable results. On the other hand, there is the possibility of hardware threats, such as tampering, reverse engineering, hardware Trojans, etc., as the design of an FIR filter involves many stages. Such hardware attacks on FIR filters can cause several problems, including performance degradation, leakage of confidential information, lack of stability, etc. This study presents the design and implementation of a Trojan-aware FIR filter using Physical Unclonable Functions (PUFs). The key feature of PUFs is that they generate a unique and unpredictable response for each given challenge. In the proposed design, PUFs were used to generate the FIR filter coefficients that are unique and unpredictable by attackers/trojans to improve security. The security of FIR with PUF was tested using ML-based challenges, and the results showed approximately 30% more reliability and consistency compared to the FIR without PUFs.

Design and implementation of two-dimensional digital finite impulse response filter using very high speed integrated circuit hardware description language

<span>The main purpose of this paper is to design a two-dimensional digital finite impulse response (FIR) filter using data broadcast and non-broadcast structure. The implementation of two-dimensional digital FIR filter is done using very high speed integrated circuit hardware description language (VHDL). Rectangular window method is used for calculating 2D digital FIR filter coefficients for data broadcast and non-broadcast structure. The coefficients of the one-dimensional digital FIR filter are obtained using the MATLAB filter design and analysis (FDA) tool for two different cut-off frequencies and are multiplied to get the necessary coefficient for the two-dimensional FIR filter to be designed; the simulation is done on Artix-7 series field programmable gate array (FPGA), target device (xc7a35t-cpg236) using Vivadov.2015.2. The proposed design reduces the area utilization and the power consumption when compared with the existing literature. The experimental result shows that the power consumption is improved by 97% and there is an improvement of 24% in area utilization for the two-dimensional with and without data broadcast one dimensional FIR filter structures.</span>

Low-Complexity Chromatic Dispersion Equalization FIR Digital Filter for Coherent Receiver

This paper proposes a novel and efficient low-complexity chromatic dispersion equalizer (CDE) based on finite impulse response (FIR) filter architecture for polarization-multiplexed coherent optical communication systems. The FIR filter coefficients are optimized by weights to reduce the energy leakage caused by the truncation effect, and then quantization is used uniformly to reduce the number of real number additions and real number multiplications by utilizing the diversity of the quantized coefficients. Using Optisystem 15 to build a coherent optical communication system for simulation and experimental demonstration, the results show that after the filter coefficients are optimized by weights. Compared with the time-domain chromatic dispersion equalizer (TD-CDE), the proposed design has a lower bit error rate (BER) and better equalization effect. When the transmission distance is 4000 km and the system quantization stages M = 16, the multiplication operation and addition operations reduce computing resources by 99% and 43%, and the BER only increases by 5%. Compared with frequency-domain chromatic dispersion equalizer (FD-CDE), widely used in long-distance communication, the multiplication operation reduces computing resources by 30%. The proposed method provides a new idea for high-performance CDE in long-distance coherent optical communication systems.

FPGA Design of a High- Resolution FIR Band-Pass Filter by Using LabVIEW Environment

Designers regularly use Finite Impulse Response (FIR) filters to fulfil the need for current electronic design applications such as signal or image processing and digital communications because of the remarkable selectivity computational efficiency. Fast and efficient information processing requires a dedicated microprocessor or a digital signal processor that may not always be available or provide enough performance. In such scenarios, designers can configure FPGAs for processing digitized signals. One of the most popular signal processing applications is filtering. Unlike the Infinite Impulse Response (IIR) filters, FIR filters do not have analog equivalent circuits. For this purpose, continuous time-discrete time conversion is not possible with the help of transforms. Because analog filters cannot have a finite impulse response, the design methods of FIR filters can be made as windowing method, pulse response truncation, and optimal filter design method. Considering this information, it aims to digitally separate two signals with different frequencies (2.4 kHz and 4.2 kHz), which are given to the input as analog, to obtain the desired information signal and suppress other signals. We preferred to use LabVIEW graphical programming language to get the digital FIR filter coefficients. We selected rectangular windowing, set the digital filter's sampling frequency as 18720 Hz, and determined the filter's coefficient with high-frequency resolution as 24. Using filter coefficients in the real-time FPGA-VHDL environment, we showed the performance and resource consumption. LabVIEW is used for simulation as well as obtaining filter coefficients. In addition, we compared both simulation and real-time FPGA-VHDL application output waveforms and examined both platforms' advantages and disadvantages.

A Novel Low-Complexity GFDM Relay Communication System: Relay Selection and Filter-and-Forward

In this paper, we develop a low-complexity cooperative relay network based on generalized frequency division multiplexing (GFDM) system. In this network, multiple relay nodes (RNs) are used to relay GFDM symbols from a source node (SN) toward a destination node (DN). We propose three methods to design the RNs based on the minimization of the total power of the noise after symbol estimation at the DN. In the first method, only one node is selected among all RNs to forward the signal from the SN to the DN. In the second and third methods, a filter-and-forward (FF) scheme is used, such that at each RN, the received GFDM signal from the SN is circularly convolved with a finite impulse response (FIR) filter and then, forwarded to the DN. The FIR filter's coefficients are represented as a circulant matrix. Since a circulant matrix is characterized by its eigenvalues, we obtain the eigenvalues of the FIR coefficient matrices for all RNs. The difference between the second and third methods is that in the former, the eigenvalues of the filter matrices are restricted to be one or zero, however, in the later, the eigenvalues are determined with no restrictions. Simulation results are provided to demonstrate the performance of the proposed methods in terms of bit error rate (BER). Moreover, we show that because of using circular convolution, the proposed methods can be implemented with a low complexity.

An Adaptive All-Pass Filter for Time-Varying Delay Estimation

The focus of this paper is the estimation of a delay between two signals. Such a problem is common in signal processing and particularly challenging when the delay is non-stationary in nature. Our proposed solution is based on an all-pass filter framework comprising of two elements: a time delay is equivalent to all-pass filtering and an all-pass filter can be represented in terms of a ratio of a finite impulse response (FIR) filter and its time reversal. Using these elements, we propose an adaptive filtering algorithm with an LMS style update that estimates the FIR filter coefficients and the time delay. Specifically, at each time step, the algorithm updates the filter coefficients based on a gradient descent update and then extracts an estimate of the time delay from the filter. We validate our algorithm on synthetic data demonstrating that it is both accurate and capable of tracking time-varying delays.

Design and optimisation of regression-type small phase shift FIR filters and FIR-based differentiators with optimal local response in LS-sense

The design of finite impulse response (FIR) filters and FIR-based differentiators is a popular topic in the field of digital signal processing. FIR filters/differentiators are characterised by a filtering architecture that does not include a feedback loop. Therefore, they are stable and have a relatively simple design, and most importantly, they can yield a filter with a linear phase diagram. Nevertheless, the FIR filter design methods reported in the scientific literature lead to a filter architecture that causes a transport delay or a nonlinear phase shift in the implementation environment. This limits the applicability of FIR filters/differentiators, e.g. in closed-loop control or real-time state estimation. In this paper, a method for FIR filter and FIR-based differentiator coefficient design is presented. The coefficients of the FIR filter and FIR-based differentiator are designed such that the FIR architecture results in a convolution leading to a locally optimal response in the least-squares sense. Thus, the FIR architecture response is characterised by an extremely small phase shift for the passband of the designed architecture. This feature results in a higher-order FIR architecture compared with the conventional design methods. In the proposed method, the delay caused by the FIR architecture is minimised by coefficient determination. Therefore, when the method is applied to a known FIR architecture, it causes a shorter delay than all other methods of coefficient determination.

Some new discrete biorthogonal wavelets constructed with Laguerre polynomials

In this study, we present a new family of discrete wavelets which are constructed with the help of Laguerre polynomials and the Daubechies biorthogonal wavelets construction method. Our aim is to propose the discrete version of some previously constructed continuous Laguerre wavelets and also to present a method of discrete wavelets construction by several iterations. With this scheme, we use two different sets of finite impulse response filters for the signal decomposition and their duals for reconstruction. The quadruplet finite impulse response filters respect the anti-aliasing and the perfect reconstruction conditions, and at the same time, they resemble as much as possible the continuous Laguerre wavelets when using the cascade algorithm. We use the mean squared error, the maximum deviation, and the standard deviation to quantify the similarity between the continuous Laguerre wavelets and the constructed discrete Laguerre wavelets. The results show that, they are both the same wavelets due to the small nature of these parameters. Our method is important because, it can permit the determination of the finite impulse response filter coefficients corresponding to many other continuous wavelets.

Decimator systolic arrays design space exploration for multirate signal processing applications

This study presents a new systolic array structure for a decimator that merges the antialiasing finite impulse response (FIR) filter with the downsampler. The development of the structure is based on a systematic methodology. Using this methodology, a dependence graph for the decimator was obtained that combined the antialiasing filter and the downsampler. Different data scheduling and projection operations were developed to obtain different proposed designs. Six systolic array design options were obtained and evaluated. The fastest design was selected for hardware implementation and compared with the other two well known decimator designs; namely, conventional design, in which the antialiasing filter is followed by a downsampling and the polyphase design, in which a commutator is followed by the polyphase antialiasing filter. Field-programmable gate array implementations for the proposed and the other two designs confirm that the proposed decimator implementation outperforms in terms of area, speed, and power as the decimation factor increases regardless of the number of FIR filter coefficients.

Exploiting Coefficient Symmetry in Conventional Polyphase FIR Filters

The conventional polyphase architecture for linear-phase finite impulse response (FIR) filter loses its coefficient symmetry property due to the inefficient arrangement of the filter coefficients among its subfilters. Although, existing polyphase structures can avail the benefits of coefficient symmetry property, at the cost of versatility and complex subfilters arrangement of the conventional polyphase structure. To address these issues, in this paper, we first present the mathematical expressions for inherent characteristics of the conventional polyphase structure. Thereafter, we use these expressions to develop a generalized mathematical framework which exploits coefficient symmetry by retaining the direct use of conventional FIR filter coefficients. Further, the transfer function expressions for the proposed Type-1/transposed Type-1 polyphase structures using coefficient symmetry are derived. The proposed structures can reduce the requirement of multiplier units in polyphase FIR filters by half. We also demonstrate the decimator design using the proposed Type-1 polyphase structure and the interpolator design using the proposed transposed Type-1 polyphase structure. Moreover, the phase and magnitude characteristics of the proposed Type-1/transposed Type-1 polyphase structures are presented. It is revealed via numerical examples that all subfilters of the proposed symmetric polyphase structure possess linear-phase characteristics.

The dynamic gammawarp auditory filterbank.

Auditory filterbanks are an integral part of many metrics designed to predict speech intelligibility and speech quality. Considerations in these applications include accurate reproduction of auditory filter shapes, the ability to reproduce the impact of hearing loss as well as normal hearing, and computational efficiency. This paper presents an alternative method for implementing a dynamic compressive gammachirp (dcGC) auditory filterbank [Irino and Patterson (2006). IEEE Trans. Audio Speech Lang. Proc. 14, 2222-2232]. Instead of using a cascade of second-order sections, this approach uses digital frequency warping to give the gammawarp filterbank. The set of warped finite impulse response filter coefficients is constrained to be symmetrical, which results in the same phase response for all filters in the filterbank. The identical phase responses allow the dynamic variation in the gammachirp filter magnitude response to be realized as a sum, using time-varying weights, of three filters that provide the responses for high-, mid-, and low-intensity input signals, respectively. The gammawarp filterbank offers a substantial improvement in execution speed compared to previous dcGC implementations; for a dcGC filterbank, the gammawarp implementation is 24 to 38 times faster than the dcGC Matlab code of Irino.

The gammawarp filterbank: A frequency-warped implementation of the dynamic compressive gammachirp filter

This paper presents an alternative method for implementing a dynamic compressive gammachirp (dcGC) auditory filterbank. Instead of using a cascade of second-order sections, the new approach uses digital frequency warping to give the gammawarp filterbank. In the warped implementation, the unit delays in a conventional finite impulse-response (FIR) filter are replaced by first-order allpass filters. The set of warped FIR filter coefficients is constrained to be symmetrical, which results in a filter phase response that is identical for all filters in the filterbank. The dynamic variation in filter response is provided by interpolating the outputs of three linear filters adjusted for low-, medium-, and high-input signal levels. The gammawarp filterbank offers a substantial improvement in execution speed compared to previous dynamic gammachirp filter implementations. For a linear filterbank, the gammawarp execution time is comparable to that of a gammatone or linear second-order section gammachirp implementation for 32 bands, but there is a processing time advantage that increases as the number of bands is increased. For a dynamic compressive gammachirp filterbank, the gammawarp implementation is 27 to 47 times faster than the dcGC MATLAB code of Irino.

FPGA Implementation of Higher Order FIR Filter

The digital Finite-Impulse-Response (FIR) filters are mainly employed in digital signal processing applications. The main components of digital FIR filters designed on FPGAs are the register bank to save the samples of signals, adder to implement sum operations and multiplier for multiplication of filter coefficients to signal samples. Although, design and implementation of digital FIR filters seem simple but the design bottleneck is multiplier block for speed, power consumption and FPGA chip area occupation. The multipliers are an integral part in FIR structures and these use a large part of the chip area. This limits the number of processing elements (PE) available on the chip to realize a higher order of filter. A model is developed in the Matlab/Simulink environment to investigate the performance of the desired higher order FIR filter. An equivalent FIR filter representation is designed by the Xilinx FIR Compiler by using the exported FIR filter coefficients. The Xilinx implementation flow is completed with the help of Xilinx ISE 14.5. It is observed how the use of higher order FIR filter impacts the resource utilization of the FPGA and it’s the maximum operating frequency.

Optimal base frequency estimation of an electrical signal based on Prony’s estimator and a FIR filter

In the frequency domain modeling of power supplying networks, it is usually necessary to determine the frequency spectrum of the currents flowing through the nonlinear devices (Arrillaga and Watson, 2003; Das, 2015; Lewandowski and Walczak, 2014). The spectrum estimation can be done in many different ways (Lewandowski and Walczak, 2014; Łobos and Rezmer, 1997; Ray et al., 2016). In work (Lewandowski and Walczak, 2014) a spectrum estimation method has been proposed, which has better accuracy in comparison with other competitive methods like WIFTA (Window Interpolated Fourier Transform) or TDQS (Time Domain Quasi-Synchronous Sampling), while maintaining a low demand for computing power. The accuracy of this method depends on two main factors: the accuracy of the fundamental frequency estimation and the accuracy of the signal interpolation in the resampling process. For the estimation of the fundamental frequency, the method uses a first order Prony’s estimator (Łobos and Rezmer, 1997) and a band-pass FIR (Finite Impulse Response) filter.In the paper, an attempt was made to find the optimal parameters for both: the Prony’s estimator and the FIR filter. First, an analysis of the measurement window size of the Prony’s estimator and the number of the FIR filter coefficients was performed. Then, the optimization problem was defined, which is not trivial, since the Prony’s estimator is highly nonlinear and some of the parameters (the window size and the number of filter coefficients) are integers. The research allowed to determine the optimal values of the considered parameters of the frequency estimation method. Along with the results presented in Lewandowski and Walczak (2015) it is now possible to implement the spectrum estimation method from Lewandowski and Walczak (2014) using the optimal set of parameters.

An approach for fixed coefficient RNS-based FIR filter

ABSTRACTIn this work, an efficient new modular multiplication method for {2k−1, 2k, 2k+1−1} moduli set is proposed to implement a residue number system (RNS)-based fixed coefficient finite impulse response filter. The new multiplication approach reduces the number of partial products by using pre-loaded product block. The reduction in partial products with the proposed modular multiplication improves the clock frequency and reduces the area and power as compared with the conventional modular multiplication. Further, the present approach eliminates a binary number to residue number converter circuit, which is usually needed at the front end of RNS-based system. In this work, two fixed coefficient filter architectures with the new modular multiplication approach are proposed. The filters are implemented using Verilog hardware description language. The United Microelectronics Corporation 90 nm technology library has been used for synthesis and the results area, power and delay are obtained with the help of Cadence register transfer level compiler. The power delay product (PDP) is also considered for performance comparison among the proposed filters. One of the proposed architecture is found to improve PDP gain by 60.83% as compared with the filter implemented with conventional modular multiplier. The filters functionality is validated with the help of Altera DSP Builder.

An Effective Allocation of Non-Zero Digits for CSD Coefficient FIR Filters Using 0-1PSO

In this paper, a novel method for effective allocation of non-zero digits in design of CSD (Canonic Signed Digit) coefficient FIR (Finite Impulse Response) filters is proposed. The design problem can be formulated as a mixed integer linear programming problem, which is well-known as a NP-hard problem. Recently, a heuristic approach using the PSO (Particle Swarm Optimization) for solving the problem has been proposed, in which the maximum number of non-zero digits is limited in each coefficient. On the other hand, the maximum number of non-zero digits is limited in total in the proposed method and the 0-1PSO is applied. It enables an effective allocation of nonzero digits and provides a good design. Several examples are shown to present an efficiency of the proposed method.

A New Separable Two-dimensional Finite Impulse Response Filter Design With Sparse Coefficients

The separable two-dimensional (2-D) finite impulse response (FIR) filter can be utilized to decrease the implementation complexity of the traditional 2-D FIR filter. A novel separable 2-D FIR filter design is proposed in this paper. The proposed design deals with a submatrix of the prototype 2-D FIR filter coefficient matrix, which contains all the information of the filter coefficient matrix. And, its basic idea is to try to utilize some column vectors of the submatrix itself to decompose this submatrix. There are zero-valued and/or one-valued coefficients in the proposed filter. In the filter implementation, these zero-valued coefficients do not require multipliers or adders. And, these one-valued coefficients do not require multipliers. Additionally, an optimal design of the general separable 2-D FIR filter in the mini-max sense and the least-square sense in the frequency domain is provided in a uniform framework, for the first time. Finally, the experimental comparison of the proposed separable 2-D FIR filter design with other separable 2-D FIR filter designs, and the comparison with other non-separable-structure low-complexity 2-D FIR filter designs are provided to validate the superiority of the proposed method.

Design and Implementation of Low-Power, Area-Efficient Fir Filter using Different Distributed Arithmetic Techniques

Background: Distributed Arithmetic (DA) technique is a bit serial operation used to perform vector to vector multiplication in convolution, which is an essential operation in digital filters. This paper presents realization of Finite Impulse Response (FIR) filters using six different DA techniques namely conventional DA, Modified DA (MDA), Offset Binary Coding DA (OBC-DA), Offset Binary Coding Modified DA (OBC-MDA) and LUT-Less DA. Methods: A novel DA method is also introduced which is a combination of multiplexers and Look-Up-Tables (LUT). In DA based FIR filter architecture the partial products of the FIR filter coefficients are pre-calculated and stored in LUTs. The filtering operation is done by shift-accumulation unit. Findings: The designs are simulated using Xilinx ISE and synthesized in Cadence RC using 180-nm technology library. From synthesis reports, it is found that for 4-tap FIR filter, Modified DA consumes 30% less power and 40% less area, whereas for 8-tap FIR filter the saving in power consumption is 30-80% and 35-80% in area. Conclusion: Compared to all the DA techniques mentioned, MDA requires least area and least power consumption because of its less memory requirement. All architectures are designed for 4-tap and 8-tap FIR filters.

An approach for FIR filter coefficient optimization using differential evolution algorithm

In this paper, we present a hardware efficient finite impulse response (FIR) filter design using differential evolution (DE) and common sub expression (CSE) elimination algorithm. With the DE algorithm, we first found a set of filter coefficients with reduced number of signed-power-of-two (SPT) terms without compromising on quality of the filter response. After obtaining coefficients, we applied CSE elimination algorithm, and determined the hardware cost in terms of adders. The filters were designed using DE for various word lengths, and the same were implemented in transposed direct form (TDF) structure. The implemented filters were synthesized in Cadence RTL compiler using UMC 90nm technology. We compared the performances of our filters with recently best published works in terms of area, delay, power and power-delay-product (PDP). One of the proposed filters found to improve a PDP gain of 29% compared to Remez algorithm. The proposed approach showed improvements in filter design for the given specifications.

Design optimisation of powers-of-two FIR filter using self-organising random immigrants GA

In this communication, we propose a novel design strategy of multiplier-less low-pass finite impulse response (FIR) filter with the aid of a recent evolutionary optimisation technique, known as the self-organising random immigrants genetic algorithm. Individual impulse response coefficients of the proposed filter have been encoded as sum of signed powers-of-two. During the formulation of the cost function for the optimisation algorithm, both the frequency response characteristic and the hardware cost of the discrete coefficient FIR filter have been considered. The role of crossover probability of the optimisation technique has been evaluated on the overall performance of the proposed strategy. For this purpose, the convergence characteristic of the optimisation technique has been included in the simulation results. In our analysis, two design examples of different specifications have been taken into account. In order to substantiate the efficiency of our proposed structure, a number of state-of-the-art design strategies of multiplier-less FIR filter have also been included in this article for the purpose of comparison. Critical analysis of the result unambiguously establishes the usefulness of our proposed approach for the hardware efficient design of digital filter.