Finite Field Inversion Research Articles

Throughput/Area Optimized Architecture for Elliptic-Curve Diffie-Hellman Protocol

This paper presents a high-speed and low-area accelerator architecture for shared key generation using an elliptic-curve Diffie-Hellman protocol over GF(2233). Concerning the high speed, the proposed architecture employs a two-stage pipelining and a Karatsuba finite field multiplier. The use of pipelining shortens the critical path which ultimately improves the clock frequency. Similarly, the employment of a Karatsuba multiplier decreases the required number of clock cycles. Moreover, an efficient rescheduling of point addition and doubling operations avoids data hazards that appear due to pipelining. Regarding the low area, the proposed architecture computes finite field squaring and inversion operations using the hardware resources of the Karatsuba multiplier. Furthermore, two dedicated controllers are used for efficient control functionalities. The implementation results after place-and-route are provided on Virtex-7, Spartan-7, Artix-7 and Kintex-7 FPGA (field-programmable gate arrays) devices. The utilized FPGA slices are 5102 (on Virtex-7), 5634 (on Spartan-7), 5957 (on Artix-7) and 6102 (on Kintex-7). In addition to this, the time required for one shared-key generation is 31.08 (on Virtex-7), 31.68 (on Spartan-7), 31.28 (on Artix-7) and 32.51 (on Kintex-7). For performance comparison, a figure-of-merit in terms of throughputarea is utilized which shows that the proposed architecture is 963.3 and 2.76 times faster as compared to the related architectures. In terms of latency, the proposed architecture is 302.7 and 132.88 times faster when compared to the most relevant state-of-the-art approaches. The achieved results and performance comparison prove the significance of presented architecture in all those shared key generation applications which require high speed with a low area.

An area-efficient architecture for finite field inversion over GF(2m) using polynomial basis

Elliptic curve cryptography (ECC) is a powerful approach to cryptography, and its implementation in cryptography necessitates a smaller chip size, lower power consumption, and faster processing. Finite-field inversion is one of the most computational operations involved in Elliptic curve cryptography(ECC). Extended-Euclidean algorithm and Itoh–Tsujii’s algorithm (ITA) are the two commonly used algorithms for implementing the FF-inversion operation. In this paper, we present the Finite-field inversion architecture developed for the modified Itoh–Tsujii’s algorithm. The reduction in computational delay for the FF-inversion is achieved by using 4k exponentiation in the realization of modified ITA. The hardware complexity of 4k exponentiation module depends on k value and k value depends on the order of the field. In this work the best value of k for a specific irreducible trinomial is computed analytically to achieve reduction in area×time product of the proposed FF-inversion architecture. The area and time complexities of the proposed architecture over National Institute of Standard and Technology(NIST) irreducible trinomials GF(2193), GF(2233), and GF(2409) targeting virtex-4 FPGA are computed and compared with similar works in the literature.

CRC-Based Error Detection Constructions for FLT and ITA Finite Field Inversions Over GF(2 m )

Binary extension finite fields ${\mathrm{ GF}}(2^{m})$ have received prominent attention in the literature due to their application in many modern public-key cryptosystems and error-correcting codes. In particular, the inversion over ${\mathrm{ GF}}(2^{m})$ is crucial for current and postquantum cryptographic applications. Schemes such as Fermat’s little theorem (FLT) and the Itoh–Tsujii algorithm (ITA) have been studied to achieve better performance; however, this arithmetic operation is a complex, expensive, and time-consuming task that may require thousands of gates, increasing its vulnerability chance to natural defects. In this work, we propose efficient hardware architectures based on cyclic redundancy check (CRC) as error detection schemes for state-of-the-art finite field inversion over ${\mathrm{ GF}}(2^{m})$ for a polynomial basis. To verify the derivations of the formulations, software implementations are performed. Likewise, hardware implementations of the original finite field inversions with the proposed error detection schemes are performed over Xilinx field-programmable gate array (FPGA) verifying that the proposed schemes achieve high error coverage with acceptable overhead.

New digital signature algorithm based on ECC and its application in bitcoin and IoT

Elliptic curve digital signature algorithm (ECDSA) is the simulation of digital signature algorithm (DSA) algorithm on elliptic curve. Compared with DSA, ECDSA has higher security and is the only widely accepted ECDSA, which has been adopted by many standardisation organisations. Based on the study of the original ECDSA scheme, this paper attempts to propose a new improved scheme. The proposed scheme has one main improvement. That is, considering that the original scheme has a finite field inversion process in the signature equation, the time-consuming inversion operation is completely avoided in the design. The proposed scheme has faster computation speed and reduces the ratio of verifying signature to signature generation time. The algorithm has certain significance for improving the efficiency of elliptic curve cryptography. Our simulation results show that the scheme runs faster and has higher signature and verification efficiency than that of the original scheme without compromising security. What's more, we also explore its application in bitcoin and Internet of Things (IoT).

An Efficient Hardware Implementation of Finite Field Inversion for Elliptic Curve Cryptography

The modular inversion operation is an essential hardware design for computing speed when we use it in cryptography applications. Through this work, we present a FSM based design methodology to achieve speed, area and high-performance modular binary inversion algorithm over 256-bit prime field. The proposed architecture implemented using Xilinx Virtex-7 FPGA device, it achieves 37% reduction in area-delay product and 15% and 16% of improvement in speed and throughput respectively, when compared with existing designs. Also, ASIC based implementation is done using TSMC 65nm CMOS technology, the synthesis results achieved the maximum operating clock frequency is 833 MHz and throughput of 626Mbps, which makes it suitable for speed-critical cryptoapplications.

Compact implementations of Curve Ed448 on low‐end IoT platforms

Elliptic curve cryptography is a relatively lightweight public-key cryptography method for key generation and digital signature verification. Some lightweight curves (eg, Curve25519 and Curve Ed448) have been adopted by upcoming Transport Layer Security 1.3 (TLS 1.3) to replace the standardized NIST curves. However, the efficient implementation of Curve Ed448 on Internet of Things (IoT) devices remains underexplored. This study is focused on the optimization of the Curve Ed448 implementation on low-end IoT processors (ie, 8-bit AVR and 16-bit MSP processors). In particular, the three-level and two-level subtractive Karatsuba algorithms are adopted for multi-precision multiplication on AVR and MSP processors, respectively, and two-level Karatsuba routines are employed for multi-precision squaring. For modular reduction and finite field inversion, fast reduction and Fermat-based inversion operations are used to mitigate side-channel vulnerabilities. The scalar multiplication operation using the Montgomery ladder algorithm requires only 103 and 73 M clock cycles on AVR and MSP processors.

Computing multiplicative inverses in finite fields by long division

Abstract We study a method of computing multiplicative inverses in finite fields using long division. In the case of fields of a prime order p, we construct one fixed integer d(p) with the property that for any nonzero field element a, we can compute its inverse by dividing d(p) by a and by reducing the result modulo p. We show how to construct the smallest d(p) with this property. We demonstrate that a similar approach works in finite fields of a non-prime order, as well. However, we demonstrate that the studied method (in both cases) has worse asymptotic complexity than the extended Euclidean algorithm.

High-speed hardware architecture for implementations of multivariate signature generations on FPGAs

Multivariate signature belongs to Multivariate-Quadratic-Equations Public Key Cryptography (MPKC), which is secure to quantum computer attacks. Compared with RSA and ECC, it is required to speed up multivariate signature implementations. A high-speed hardware architecture for signature generations of a multivariate scheme is proposed in this paper. The main computations of signature generations of multivariate schemes are additions, multiplications, inversions, and solving systems of linear equations (LSEs) in a finite field. Thus, we improve the finite field multiplications via using composite field expression and design a finite field inversion via using binary trees. Besides, we improve solving LSEs in a finite field based on a variant algorithm of Gauss-Jordan elimination and use the XOR gates to compute additions. We implement the high-speed hardware architecture based on the above improvements on an Altera Stratix Field-Programmable Gate Array (FPGA), which shows that it takes only 90 clock cycles and 0.9 μs to generate a multivariate signature. The comparison shows that the hardware architecture is much faster than other implementations.

Linear combinations of primitive elements of a finite field

We examine linear sums of primitive roots and their inverses in finite fields. In particular, we refine a result by Li and Han, and show that every p>13 has a pair of primitive roots a and b such that a+b and a−1+b−1 are also primitive roots mod p.

Unified systolic array architecture for finite field multiplication and inversion

This paper proposes a new unified systolic array architecture to perform multiplication and inversion operations in GF(2m) based on the bit serial multiplication algorithm and the previously modified extended Euclidean algorithm. This architecture is explored by applying a regular technique to the multiplication and inversion algorithms. It has lower area and power complexities as well as it achieves a moderate speed. Also, it has a simple structure with processing elements have local communication with each other. The implementation results of the proposed design and the comparable published designs show that the proposed design saves more area (ranging from 18.8% to 23.0%) and saves more energy (ranging from 18.2% to 47.0%) over the compared efficient designs. This makes it more suitable for applications that impose more constraints on area and power consumption.

Bandwidth Overhead-Free Data Reconstruction Scheme for Distributed Storage Code With Low Decoding Complexity

The $(n,k)$ combination property (CP) is defined as follows: $k$ source packets are mapped into $n \geq k$ packets and any $k$ out of these $n$ packets are able to recover the information of the original $k$ packets. This $(n,k)$ CP is extensively needed by cloud storage service providers. Reed-Solomon (RS) codes possess CP at the cost of high encoding and decoding complexity for two reasons: operation over a large-size finite field and time-consuming matrix inversion operation. By operating within the binary field and by allowing only zigzag decoding at the decoder, binary zigzag decoding that possesses CP lowers the decoding complexity significantly. The drawback is that storage room overhead is needed. Corresponding to this storage room overhead, in the data reconstruction process, intuitively fetching $k$ whole stored packets will consume overhead bandwidth. In this paper, a data reconstruction scheme that is optimal in terms of bandwidth consumption is designed, where optimal means the bandwidth consumption is equal to the volume of data to be reconstructed, namely, no overhead bandwidth is needed. To do that, a universal method of fetching sub-packet is proposed, and its corresponding decoding method is also designed.

Accelerating Finite Field Inversion in GF(3m) for Elliptic Curve Cryptography

Accelerating Finite Field Inversion in GF(3m) for Elliptic Curve Cryptography

Reversed genetic algorithms for generation of bijective s-boxes with good cryptographic properties

Often the S-boxes are the only nonlinear components in a block cipher and as such play an important role in ensuring its resistance to cryptanalysis. Cryptographic properties and constructions of S-boxes have been studied for many years. The most common techniques for constructing S-boxes are: algebraic constructions, pseudo-random generation and a variety of heuristic approaches. Among the latter are the genetic algorithms. In this paper, a genetic algorithm working in a reversed way is proposed. Using the algorithm we can rapidly and repeatedly generate a large number of strong bijective S-boxes of each dimension from (8 × 8) to (16 × 16), which have sub-optimal properties close to the ones of S-boxes based on finite field inversion, but have more complex algebraic structure and possess no linear redundancy.

Fast and Generic Inversion Architectures Over $\mbox{GF}(2^m)$ Using Modified Itoh–Tsujii Algorithms

Finite field inversion is the most computationally intensive field operation in public-key cryptographic algorithms such as elliptic curve cryptography. In this brief, we propose two inversion acceleration techniques for the Itoh–Tsujii algorithm (ITA) over binary extended field. First, we reformulate the ternary-ITA algorithm to generalize the primitive one, so that a universal algorithm procedure for all fields is achieved. Next, we devise a parallel-ITA algorithm to advance the parallelism of ITA. These two techniques are implemented on FPGA platform, and it is experimentally shown that a fast ternary-ITA inverter supporting all NIST fields can be obtained, with 22.9% timing improvement on average compared to the ITA inverter. In addition, the parallel-ITA inverter is a more balancing design that achieves averagely 25.7% of timing decrease compared to the ITA inverter while maintaining 31.3% reduction of area-time product compared to the ternary-ITA inverter.

Design and Implementation of SM4 Block Cipher Based on Composite Field

In this paper, a new method based on composite field is proposed. Through isomorphism bit matrices, the calculation by changing finite field inversion from GF(28) to GF(((22)2)2) is simplified to reduce the computational difficulty and a more compact S-box is realized. The area decreases by 27% than Look-up Table. On the basis of that, the SM4 algorithm is implemented. The area of this IP core is only 7 612 gates synthesized under the smic0.13 μmCMOS process. Therefore this improved design is very helpful for area-limited condition such as IC cards.

Fast Inversion in <formula formulatype="inline"><tex Notation="TeX">${\schmi{GF(2^m)}}$</tex></formula> with Normal Basis Using Hybrid-Double Multipliers

Fast inversion in finite fields is crucial for high-performance cryptography and codes. We present techniques to exploit the recently proposed hybrid-double multipliers for fast inversions in binary fields GF(2m) with normal bases. A hybrid-double multiplier computes a double multiplication, the product of three elements in GF(2m), with a latency comparable to the latency of single multiplication of two elements. Traditional approaches, such as Itoh-Tsujii, cannot utilize hybrid-double multipliers. We devise a new inversion algorithm based on ternary representations that exploits their potential. The algorithm reduces the latency of inversion significantly for the fields recommended by NIST if hybrid-double multipliers are employed. For example, the algorithm computes an inversion in GF(2163) with only five double multiplications whereas the Itoh-Tsujii algorithm requires nine single or double multiplications. We propose a new inverter architecture using this new algorithm and a hybrid-double multiplier. We show that it is faster than the existing techniques by providing ASIC synthesis results using 65-nm CMOS technology. For example, our inverter for GF(2163) achieves about 34 percent shorter computation time than an inverter using the Itoh-Tsujii algorithm and a single multiplier.

Extended elliptic curve Montgomery ladder algorithm over binary fields with resistance to simple power analysis

In this paper, we propose a scalar multiplication algorithm on elliptic curves over GF(2m). The proposed algorithm is an extended version of the Montgomery ladder algorithm with the quaternary representation of the scalar. In addition, in order to improve performance, we have developed new composite operation formulas and apply them to the proposed scalar multiplication algorithm. The proposed composite formulas are 2P1+2P2, 3P1+P2, and 4P1, where P1 and P2 are points on an elliptic curve. They can be computed using only the x-coordinate of a point P=(x,y) in the affine coordinate system. However, the proposed scalar multiplication algorithm is vulnerable to simple power analysis attacks, because different operations are performed depending on the bits of the scalar unlike the original Montgomery ladder algorithm. Therefore, we combine the concept of the side-channel atomicity with the proposed composite operation formulas to prevent simple power analysis. Furthermore, to optimize the computational cost, we use the Montgomery trick which can reduce the number of finite field inversion operations used in the affine coordinate system. As the result, the proposed scalar multiplication algorithm saves at least 26% of running time with small storage compared to the previous algorithms such as window-based methods and comb-based methods.

A new method to determine algebraic expression of power mapping based S-boxes

Power mapping based S-boxes, especially those with finite field inversion, have received significant attention by cryptographers. S-boxes designed by finite field inversion provide good cryptographic properties and are used in most ciphersʼ design such as Advanced Encryption Standard (AES), Camellia, Shark and others. However, such an S-box consists of a simple algebraic expression, thus the S-box design is completed by adding an affine transformation before the input of the S-box, or after the output of the S-box or both in order to make the overall S-box description more complex in a finite field.In the present study, a new method of computation of the algebraic expression (as a polynomial function over GF(28)) of power mapping based S-boxes designed by three different probable cases is described in which the place of the affine transformation differs. The proposed method is compared with the Lagrange interpolation formula with respect to the number of polynomial operations needed. The new method (based on the square-and-multiply technique) is found to reduce time and polynomial operation complexity in the computation of the algebraic expression of S-boxes.

Generalized high speed Itoh–Tsujii multiplicative inversion architecture for FPGAs

Among all finite field operations, finite field inversion is the most computationally intensive operation. Yet, it is an essential component of several public-key cryptographic algorithms such as elliptic curve cryptography. For hardware implementations over extended binary fields, the Itoh–Tsujii inversion algorithm (ITA) is the most efficient. In this paper we propose acceleration techniques for ITA on FPGA platforms. We first propose a generalization of the parallel ITA which uses exponentiation by 2n and 2n, where n≥1. Parallel ITA has several drawbacks which limit its speed. We propose a novel technique supported with theoretical analysis to overcome the drawbacks. The technique reduces the critical delay of the ITA architecture without increasing the clock cycle requirement. Experimental results are presented to show that the proposed technique outperforms reported results.

Cryptographic properties of modified AES-like S-boxes

Using AES-like S-boxes (generated using finite field inversion) provides an excellent starting point for generating S-boxes with some specific design criteria dictated by the implemented cipher and still maintaining all the most commonly recognized cryptographic criteria to a large extent. This paper presents the results of statistical analysis of fulfilment of those basic cryptographic criteria by the modified AES-like S-boxes that do have neither equivalence nor cycles.