FinFET Logic Circuits Research Articles

Integrating flipped drain and power gating techniques for efficient FinFET logic circuits

AbstractPower dissipation is a main attention for designing complementary metal oxide semiconductor Very Large Scale Integration (VLSI) circuits in deep sub‐micron technology. Constant field device scaling leads to high transistor density, reduction in power supply, lower threshold voltage, and reduction in oxide thickness. This gives rise to short channel effects and increases the leakage currents causing power dissipation. In this paper, based on literature survey, new flipped drain gating (FDG) technique is proposed for mitigation of leakage currents; further FDG technique is integrated with power gating technique which makes power dissipation lower than FDG. Proposed techniques are integrated with FinFET technology and applied on Logic Gates and bench mark circuits on HSPICE simulator. Simulation is carried out at 27°C temperature by using 20 to 7‐nm Berkley Predictive Technology Module. Simulation results at 10‐MHz frequency shows maximum saving in leakage power using FDG technique at input vector 01 as 80.35% compared with conventional drain gating for EXOR logic. Similarly, FDG technique saves maximum dynamic power of 25.98% when compared with conventional drain gating for AND logic.

Delay/Power Modeling and Optimization of FinFET Circuit Modules under PVT Variations

The semiconductor industry has moved to FinFETs because of their superior ability to mitigate short-channel effects relative to CMOS. Thus, good FinFET delay and power models are urgently needed to facilitate FinFET IC design at the upcoming technology nodes. Another urgent problem that needs to be addressed with continued technology scaling is how to analyze circuit performance and power consumption under process, voltage, and temperature (PVT) variations. Such variations arise due to limitations of lithography that lead to variations in the physical dimensions of the device or due to environmental variations. In this article, we propose a delay/power modeling framework for analysis of FinFET logic circuits under PVT variations. We present models for FinFET logic gates and three FinFET SRAM cells. We use GenFin, which is a genetic algorithm based statistical circuit-level delay/power optimizer, to produce the models for functional units (FUs) employed in a processor. We compare the impact of PVT variations at the 22nm and 14nm FinFET technology nodes. We evaluate cache performance for various cache capacities and temperatures as well as that of FUs. Our device simulation results show that the 3σ/μ spread for 14nm circuits is, on average, 38.5% higher in dynamic power and 21.4% higher in logarithm of leakage power relative to 22nm FinFET circuits. However, the delay spread depends on the circuit.

Low-power Super-threshold FinFET Domino Logic Circuits for High- Speed Applications

Domino logic circuits have faster operating speed than commonly used static logic ones, because they have lower input capacitances and no contention during transition. However, Domino logic circuits have more power dissipa- tion than static logic ones, since their clock tress with high switch activity dissipates large energy. A low-power super- threshold computing scheme is proposed to reduce power dissipations of FinFET Domino logic circuits. The pull-down transistors of all FinFET Domino circuits are configured in parallel, and thus improve operating speed. Unlike near- threshold circuits, super-threshold ones are supplied by much a larger supply voltage than the threshold voltage, but it is lower than the standard supply voltage. Super-threshold FinFET logic circuits can attain low power consumption with fa- vorable performance, because FinFET devices operating on medium strong inversion regions can provide better drive strength than conventional CMOS ones. The basic Domino logic gates are compared with static logic ones in terms of en- ergy consumption, delay, energy delay product (EDP), and maximum operation frequency with different voltages from near-threshold to super-threshold regions. All circuits are simulated with HSPICE at a PTM (Predictive Technology Mod- el) 32nm FinFET technology. The results show that the Domino gates can operate faster than static ones. In addition, it is also shown that Domino gates exhibit the best EDP in super-threshold regions (about 700mV). Compared with the stand- ard supply voltage of 1.0 V, the Domino gates supplied by 0.8V can attain energy reductions of more than 38.3% with a small performance penalty of about 14%.

FinPrin: FinFET Logic Circuit Analysis and Optimization Under PVT Variations

Continued scaling of bulk CMOS technology is facing formidable challenges. FinFETs, with better control of short-channel effects, offer a promising alternative for the 22-nm technology node and beyond. However, FinFETs still suffer from process, voltage, and temperature (PVT) variations. Thus, to analyze the delay of FinFET logic circuits, statistical static timing analysis (SSTA) is more suitable than traditional static timing analysis. In this paper, using an existing SSTA algorithm as a foundation, we analyze silicon-on-insulator FinFET circuits in various new ways: basing the analysis on accurate device simulation of the logic library; considering voltage and temperature variations, in addition to process variations; deriving accurate timing and leakage macromodels; and investigating the impact of PVT variations on delay/leakage distributions at the circuit level. We propose a simplified timing model that greatly reduces the computational complexity without giving rise to any convergence issues. The timing model has an average absolute error of 3.4% and 4.4%, respectively, for gate output slope and gate delay over all logic gates and sizes, compared with accurate quasi-Monte Carlo simulations. We evaluate the performance of our SSTA algorithm with respect to Monte Carlo simulation, and extend the algorithm to enable statistical leakage and dynamic power analysis as well. We investigate the impact of PVT variations on delay/power distributions at the circuit level. We show that deterministic optimization methods can optimize both the mean and variance of circuit delay/power distributions, and even the ratio of standard deviation to mean in some cases. Finally, we show that FinFET circuits need to be carefully optimized with temperature taken into consideration, since the ratio between the leakage and dynamic power of a circuit can vary drastically depending on the operating temperature assumed.

Understanding the Basic Advantages of Bulk FinFETs for Sub- and Near-Threshold Logic Circuits From Device Measurements

This study aims to understand the potential of bulk FinFET technology from the perspective of sub- and near-threshold logic circuits down to 100-mV bias voltage. Measurements are performed on bulk FinFETs with a channel length of 60 nm, a fin height of 33 nm, and a fin width of only 14 nm and with a high- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$k$</tex></formula> /metal-gate stack having an equivalent thickness in inversion of 1.6 nm. For comparison purposes, measurements are also performed on bulk planar FETs with the same channel length and similar gate stack. FinFETs show a stronger dependence of the drain current on the gate voltage and a lower dependence on the drain and body biases w.r.t. planar devices. After adjusting for the different threshold voltages, FinFETs exhibit perfect balance between n- and p-FETs at any applied bias in the sub- and near-threshold regimes. As a consequence, FinFET logic circuits have significantly improved voltage scalability from the perspective of dc robustness and of performance/energy.

Leakage–Delay Tradeoff in FinFET Logic Circuits: A Comparative Analysis With Bulk Technology

In this paper, we study the advantages offered by multi-gate fin FETs (FinFETs) over traditional bulk MOSFETs when low standby power circuit techniques are implemented. More precisely, we simulated various vehicle circuits, ranging from ring oscillators to mirror full adders, to investigate the effectiveness of back biasing and transistor-stacking in both FinFETs and bulk MOSFETs. The opportunity to separate the gates of FinFETs and to operate them independently has been systematically analyzed; mixed connected- and independent-gate circuits have also been evaluated. The study spans over the device, the layout, and the circuit level of abstraction and appropriate figures of merit are introduced to quantify the potential advantage of different schemes. Our results show that, thanks to a larger threshold voltage sensitivity to back biasing, the FinFET technology is able to offer a more favorable compromise between standby power consumption and dynamic performance and is well suited for implementing fast and energy-efficient adaptive back-biasing strategies.