Fine-grained Parallel Programming Research Articles

Construction of College Students’ Mental Health Education Model Based on Data Analysis

This paper presents an in-depth study and analysis of the model of college students’ mental health education using fine-grained parallel computational programming. In the experimental group, the total level of positive thoughts and the level of life satisfaction significantly increased and the level of depression significantly decreased before and after the implementation of the intervention; in the control group, the level of life satisfaction significantly increased before and after the implementation of the intervention, and there was no significant difference in the total level of positive thoughts and the level of depression. Based on the above results, the positive thinking group-assisted training in this study was effective in improving the level of positive thinking and life satisfaction and reducing the level of depression into two categories of high school students: those who were susceptible and those who were symptomatic but satisfied, thus improving their mental health status, and may provide operational references for future intervention studies. At the same time, some studies have pointed out that when college students are faced with stressful situations, they will have higher psychological levels if they take a positive way to deal with them, and when college students are under stress, they will use a positive psychological restraint mechanism to cope. From a macroperspective, the research results can also be used to guide the training system of mental health education teachers, teachers’ professional development, and career development planning, showing certain application value.

Degree-of-Node Task Scheduling of Fine-Grained Parallel Programs on Heterogeneous Systems

Processor specialization has become the development trend of modern processor industry. It is quite possible that this will still be the main-stream in the next decades of semiconductor era. As the diversity of heterogeneous systems grows, organizing computation efficiently on systems with multiple kinds of heterogeneous processors is a challenging problem and will be a normality. In this paper, we analyze some state-of-the-art task scheduling algorithms of heterogeneous computing systems and propose a Degree of Node First (DONF) algorithm for task scheduling of fine-grained parallel programs on heterogeneous systems. The major innovations of DONF include: 1) simplifying task priority calculation for directed acyclic graph (DAG) based fine-grained parallel programs which not only reduces the complexity of task selection but also enables the algorithm to solve the scheduling problem for dynamic DAGs; 2) building a novel communication model in the processor selection phase that makes the task scheduling much more efficient. They are achieved by exploring finegrained parallelism via a dataflow program execution model, and validated through experimental results with a selected set of benchmarks. The results on synthesized and real-world application DAGs show a very good performance. The proposed DONF algorithm significantly outperforms all the evaluated state-of-the-art heuristic algorithms in terms of scheduling length ratio (SLR) and efficiency.

Robust Massively Parallel Dynamic State Estimation of Power Systems Against Cyber-Attack

The evolution of traditional energy networks toward smart grids increases security vulnerabilities in the power system infrastructure. State estimation plays an essential role in the efficient and reliable operation of power systems, so its security is a major concern. Coordinated cyber-attacks, including false data injection (FDI) attack, can manipulate smart meters to present serious threats to grid operations. In this paper, a robust state estimation algorithm against FDI attack is presented. As a solution to mitigate such an attack, a new analytical technique is proposed based on the Markov chain theory and Euclidean distance metric. Using historical data of a set of trusted buses, a Markov chain model of the system normal operation is formulated. The estimated states are analyzed by calculating the Euclidean distance from the Markov model. States, which match the lower probability, are considered as attacked states. It is shown that the proposed method is able to detect malicious attack, which is undetectable by traditional bad data detection (BDD) methods. The proposed robust dynamic state estimation algorithm is built on a Kalman filter, and implemented on the massively parallel architecture of graphic processing unit using fine-grained parallel programming techniques. Numerical simulations demonstrate the efficiency and accuracy of the proposed mechanism.

The home-forwarding mechanism to reduce the cache coherence overhead in next-generation CMPs

On the road to computer systems able to support the requirements of exascale applications, Chip Multi-Processors (CMPs) are equipped with an ever increasing number of cores interconnected through fast on-chip networks. To exploit such new architectures, the parallel software must be able to scale almost linearly with the number of cores available. To this end, the overhead introduced by the run-time system of parallel programming frameworks and by the architecture itself must be small enough in order to enable high scalability also for very fine-grained parallel programs. An approach to reduce this overhead is to use non-conventional architectural mechanisms revealing useful when certain concurrency patterns in the running application are statically or dynamically recognized. Following this idea, this paper proposes a run-time support able to reduce the effective latency of inter-thread cooperation primitives by lowering the contention on individual caches. To achieve this goal, the new home-forwarding hardware mechanism is proposed and used by our runtime in order to reduce the amount of cache-to-cache interactions generated by the cache coherence protocol. Our ideas have been emulated on the Tilera TILEPro64 CMP, showing a significant speedup improvement in some first benchmarks.

Towards a First Vertical Prototyping of an Extremely Fine-Grained Parallel Programming Approach

Explicit multithreading (XMT) is a parallel programming approach for exploiting on-chip parallelism. XMT introduces a computational framework with (1) a simple programming style that relies on fine-grained PRAM-style algorithms; (2) hardware support for low-overhead parallel threads, scalable load balancing, and efficient synchronization. The missing link between the algorithmic-programming level and the architecture level is provided by the first prototype XMT compiler. This paper also takes this new opportunity to evaluate the overall effectiveness of the interaction between the programming model and the hardware, and enhance its performance where needed, incorporating new optimizations into the XMT compiler. We present a wide range of applications, which written in XMT obtain significant speedups relative to the best serial programs. We show that XMT is especially useful for more advanced applications with dynamic, irregular access patterns, where for regular computations we demonstrate performance gains that scale up to much higher levels than have been demonstrated before for on-chip systems.

RECOGNIZING K-ROTATED SEGMENTS

This paper explains a calculational design technique for fine-grained parallel programs by means of an example. The example deals with the recognition of K-rotation invariant (or K-rotated) segments which is a generalization of the well known square recognition problem. Two parallel programs are derived. The first one determines for each segment of N successive inputs whether it is K-rotated, the latter determines whether the whole sequence thus far received is K-rotated.

Evaluation of mechanisms for fine-grained parallel programs in the J-machine and the CM-5

This paper uses an abstract machine approach to compare the mechanisms of two parallel machines: the J-Machine and the CM-5. High-level parallel programs are translated by a single optimizing compiler to a fine-grained abstract parallel machine, TAM. A final compilation step is unique to each machine and optimizes for specifics of the architecture. By determining the cost of the primitives and weighting them by their dynamic frequency in parallel programs, we quantify the effectiveness of the following mechanisms individually and in combination. Efficient processor/network coupling proves valuable. Message dispatch is found to be less valuable without atomic operations that allow the scheduling levels to cooperate. Multiple hardware contexts are of small value when the contexts cooperate and the compiler can partition the register set. Tagged memory provides little gain. Finally, the performance of the overall system is strongly influenced by the performance of the memory system and the frequency of control operations.

Parallel Processing Implications for Management Scientists

As parallel processing systems become more accessible, management scientists need to be aware of their implications for algorithm design. Parallel processing systems can simultaneously execute several programs and can be categorized by the number of processors available or the number of data streams that can be used. Efficient interprocessor communication is essential. Fine-grained parallel programs explicitly make use of these communication functions to improve speed, while coarse-grained programs interact less frequently and distribute similar subprograms among processors. In either case, procedures can be used to enable serial programs to execute on parallel processors. Management scientists have used these systems to investigate linear programming problems, simulation models, and network analysis. They offer users opportunities to address problems whose solutions were previously limited by serial-processing architectures.