Fifth-order Elliptic Low-pass Filter Research Articles

Configuration for a grounded lossy impedance simulator employing CC-CFAs and grounded passive elements

This article presents a configuration that can simulate both a resistor in series with a frequency-dependent negative-resistance (R-D) and a resistor in series with a capacitor (R-C), with a different selection of passive elements. The proposed circuit employs only two current-controlled-current-feedback- amplifiers (CC-CFAs) and grounded passive elements. This configuration does not require passive element matching, and the simulated equivalent element values can be tuned electronically by applying a biasing current to the CC-CFAs. To demonstrate the application of the proposed grounded series R-D impedance simulator, it is applied to a second-order notch filter and a fifth-order elliptic lowpass filter, whereas the series R-C impedance simulator is applied to a secondorder resonance circuit to find the band-pass response of the input current. Our theoretical analysis is confirmed by the results of a PSPICE simulation.

A New Lowpass Filter Unit Cell with Sharp Roll-off and Improved Stopband Performance in Coplanar Waveguide Technology

In this paper, a new compact unit cell for a coplanar waveguide (CPW) lowpass filter (LPF) is proposed. By combining a pair of coupled parallel stepped impedance resonators (SIRs) and high impedance short stubs in the CPW line, a fifth-order elliptic lowpass filter unit cell (LUC) is designed. The extra transmission zero introduced by parallel coupled SIRs is used to extend the stopband and increase the roll-off rate. The characteristics of the proposed LUC is investigated to achieve a sharp roll-off and a wide stopband. The measured results are in accordance with the simulated results. It has an insertion loss less than 0.9 dB from dc to 6 GHz, and a wide -15 dB stopband from 7.5 to 18 GHz. In addition, the filter dimensions are as small as 4.9 mm × 8.7 mm, that is, 0.046λg2, where λg is the guided wavelength at the cut-off frequency. The filter structure is simple and easy to fabricate as well.

Nano-scale area-efficient Gm–C filters using MOS capacitors

ABSTRACTThe rapid growth of scaling and integration of nano-scale digital circuits is hardly tracked by the analog circuits which require additional passive components for fabrication. Mixed-signal Complementary Metal Oxide Semiconductor (CMOS) technologies are released with some delays after digital CMOS technologies, due to the issues related to integration of analog components. This urges the designers to consider using the same digital CMOS technology for integration of advanced analog circuits like continuous-time filters. As such, this article presents an area-efficient Gm–C filter made from MOS devices only. Instead of classical metal–insulator–metal capacitors, the proposed filter exploits the available compact-size MOS devices as capacitor. This modification makes the filter design compatible to any low-cost digital CMOS process. Besides, the 3-dB cut-off frequency of the filter can now be changed by varying the size of MOS capacitors. The effectiveness of the new design approach is validated through simulation of a fifth-order elliptic low-pass filter with a cut-off frequency of 1 MHz in 90-nm CMOS technology. The new filter dissipates around 115 µW from a 1.0 V power supply, and the sensitivity of its cut-off frequency is kept as low as 6% over various process and temperature corners.

Low‐voltage fully differential difference transconductance amplifier

A new complementary metal-oxide-semiconductor (CMOS) structure for fully differential difference transconductance amplifier (FDDTA) is presented in this study. Thanks to using the non-conventional quasi-floating-gate (QFG) technique the circuit is capable to work under low-voltage supply of 0.6 V with extended input voltage range and with class AB output stages. The QFG multiple-input metal-oxide-semiconductor transistor is used to reduce the count of the differential pairs that needed to realise the FDDTA with simple CMOS structure. The static power consumption of the proposed FDDTA is 40 μW. The FDDTA was designed in Cadence platform using 0.18 μm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC). As an example of applications a three-stage quadrature oscillator and fifth-order elliptic low-pass filter are presented to confirm the attractive features of the proposed CMOS structure of the FDDTA.

A Wide Tuning Range <formula formulatype="inline"><tex>$G_{m}$</tex> </formula>–<formula formulatype="inline"><tex>$C$</tex></formula> Continuous-Time Analog Filter

A CMOS operational transconductance amplifier (OTA) for low-power and wide tuning range filter application is proposed in this paper. The OTA can work from the weak inversion region to the strong inversion region to maximize the transconductance tuning range. The transconductance can be tuned by changing its bias current. A fifth-order Elliptic low-pass filter implemented with the OTAs was integrated by TSMC 0.18-mum CMOS process. The filter can operate with the cutoff frequency of 250 Hz to 1 MHz. The wide tuning range filter would be suitable for multi-mode applications, especially under the consideration of saving chip areas. The third-order inter-modulation (IM3) of -40 dB was measured over the tuning range with two tone input signals. The power consumption is 0.8 mW at 1-MHz cutoff frequency and 1.8-V supply voltage with the active area less than 0.3 mm2

0.5-V analog circuit techniques and their application in OTA and filter design

We present design techniques that make possible the operation of analog circuits with very low supply voltages, down to 0.5 V. We use operational transconductance amplifier (OTA) and filter design as a vehicle to introduce these techniques. Two OTAs, one with body inputs and the other with gate inputs, are designed. Biasing strategies to maintain common-mode voltages and attain maximum signal swing over process, voltage, and temperature are proposed. Prototype chips were fabricated in a 0.18-/spl mu/m CMOS process using standard 0.5-V V/sub T/ devices. The body-input OTA has a measured 52-dB DC gain, a 2.5-MHz gain-bandwidth, and consumes 110 /spl mu/W. The gate-input OTA has a measured 62-dB DC gain (with automatic gain-enhancement), a 10-MHz gain-bandwidth, and consumes 75 /spl mu/W. Design techniques for active-RC filters are also presented. Weak-inversion MOS varactors are proposed and modeled. These are used along with 0.5-V gate-input OTAs to design a fully integrated, 135-kHz fifth-order elliptic low-pass filter. The prototype chip in a 0.18-/spl mu/m CMOS process with V/sub T/ of 0.5-V also includes an on-chip phase-locked loop for tuning. The 1-mm/sup 2/ chip has a measured dynamic range of 57 dB and draws 2.2 mA from the 0.5-V supply.

Log-domain filtering by simulating the topology of passive prototypes

A systematic method for designing log-domain filter structures that simulate the topology of the corresponding passive prototypes is introduced in this paper. This has been achieved by transposing the i-/spl upsi/ characteristic equation of each passive element in the linear domain, to the corresponding one in the log domain. The transposition has been done in such a way that, the current that flows through the terminals of the passive element in the linear domain sustains its value in the corresponding log-domain configuration. In this way the linear operation of the whole filter is preserved. With regard to the voltage at each terminal of the passive prototype, this is logarithmically compressed in order to achieve filtering in the log domain. Following the above considerations, the log-domain equivalents of all passive elements of the prototype filter were derived. Having established the equivalents, the procedure for designing high-order log-domain filters is quite facilitated. The validity of the proposed technique is demonstrated through simulation results for a fifth-order elliptic low-pass filter.

Efficient design of ladder-based transconductor-capacitor filters and equalisers

The paper outlines matrix methods for ladder-based transconductor-capacitor filter and equaliser design and a theory for the canonical realisation of ladder-based transconductor-C filter is presented. A filter and equaliser compiler based on the proposed method is described. As an example, a fifth-order elliptic lowpass filter and a sixth-order group delay equaliser have been designed. It is shown that the order of the equaliser can be reduced by application of special techniques for the approximation of the filter transfer function. A comparison of sensitivity between a cascade of biquadratic stages and the ladder-based realisation is given. Lower sensitivities to component tolerance for both filter and equaliser are displayed by the ladder-based design. Test results from the fabricated filter and equaliser are also given.