Field Programmable Gate Array Structure Research Articles

An FPGA-based online reconfigurable CNN edge computing device for object detection

Edge devices offer advantages such as low computation latency and high data security for executing convolutional neural networks (CNNs). However, deploying CNNs on resource-constrained devices is challenging due to the high computational intensity of CNNs and limited hardware on-chip resources. This hinders the application of deep learning techniques on edge devices. To address this issue, this paper proposes a reconfigurable CNN edge computing system based on Field-Programmable Gate Array (FPGA) for target detection tasks. The system utilizes the pipeline structure of FPGAs to speed up network computation and employs off-chip memory to store network models. Thus, the need for tiling techniques with high intermediate cache requirements was circumvented in this system. Additionally, we developed a parallel data scheduling model to reduce storage access cost delay on network computation efficiency. Our model achieves comparable efficiency with on-chip storage-based works when using off-chip storage. Online reconfigurable design enables the system to configure network structure and parameters at runtime to achieve different target recognition. This provides greater flexibility for use cases with frequently changing requirements. The proposed system was implemented on a Spartan-6 XC6SLX150 FPGA platform and was applied to pedestrian and vehicle classification tasks. To evaluate performance, speed, power consumption, and average intersection over union (IoU) were separately measured. Our system achieved a detection speed of 16 frames per second (FPS) on the Spartan-6, with a power consumption rate of 0.79 W and an average IoU of 41.2%. Remarkably, the system demonstrated a 178% speed increase and a 60% power consumption reduction compared to the FPGA-based FitNN implementation, while classification accuracy was reduced by only 2.52%.

Increasing Energy Efficiency With Fuzzy Logic Control in FPGA-Based Electromagnetic Stirrer

In this study, a new field-programmable gate array (FPGA)-based electromagnetic stirrer system was developed allowing mixing on a single axis, and the energy efficiency of the system was increased with fuzzy logic control. The electromagnetic stirrer system was designed with three phases and each phase is fed with pulsewidth modulation (PWM) voltage with 120° phase difference. Ranked control of phases in the system used the FPGA structure in the myRIO® embedded system to determine the PWM signal production, increase intervals for phase frequencies, and rotation rate of the magnetic stir bar. In the system, to increase the energy efficiency with fuzzy logic control, the ARM® microcontroller structure in the myRIO® embedded system was used. Programming of the myRIO® embedded system was provided through the graphic-based LabVIEW <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">®</sup> software. In situations where the system is operated with 100% duty cycle, the force affecting the magnetic stir bar should be continuous and have fixed value until the next phase change. As a result, the magnetic stir bar performs more than 120° rotation and a braking effect of the force is observed. To resolve this situation, fuzzy logic control ensured operation of a different duty cycle without loss of speed of the stir bar. Thus, the energy efficiency of the system was increased with lower current and lower stimulation duration. Within the scope of this article, the experimental results obtained about the structure, control, and energy efficiency of the electromagnetic stirrer system are discussed in detail.

Multi-Channel Data Acquisition Card under New Acquisition and Transmission Architecture of High Frequency Ground Wave Radar

It is known that the data acquisition and processing system plays an important role in radar target detection system. In order to meet the requirements of real-time processing and accurate transmission of echo signals in high-frequency ground-wave radar (HFGWR) systems, a new acquisition and transmission framework utilizing the designed acquisition card based on the PCIe (peripheral component interconnect express) has been designed and is presented in this paper. The Xilinx FPGA (Field-Programmable Gate Array) chip Kintex7-XC7K325T is adopted as a hardware carrier in acquisition card. The hardware’s composition, analog front-end circuit, the DMA (Direct Memory Access) transmission, FPGA structure, ADC (Analog-to-Digital Converter) chip, and performance test of this card are showed and discussed. Currently, the acquisition card has been accomplished and applied in the practical system of HFGWR.

A Task-Schedulable Nonvolatile Spintronic Field-Programmable Gate Array

Despite the vast hardware resources available in field-programmable gate arrays (FPGAs), the implementation of very large and complex designs on these platforms is a challenging problem. One effective solution is to use task scheduling. In this method, the FPGA configuration is changed according to the required task. This requires access to external nonvolatile memory, which significantly reduces system performance. In this letter, the development of a nonvolatile spintronic FPGA structure with task-scheduling capability is described. By using the nonvolatile feature of the magnetic tunnel junction device, the structure can store two different configurations in a nonvolatile way, which eliminates the need for external memory access and significantly enhances system performance.

Watermark Decoding Technique using Machine Learning for Intellectual Property Protection

The Watermarking is an Intellectual Property (IP) Protection method. It can ensure Field-Programmable Gate Array (FPGA) IPs from encroachment. The IP security of equipment and programming structures is the most significant prerequisite for some FPGA licensed innovation merchants. Advanced watermarking has become a creative innovation for IP assurance as of late. This paper proposes the Publicly Verifiable Watermarking plan for licensed innovation insurance in FPGA structure. The Zero-Knowledge Verification Protocol and Data Matrix strategy are utilized in this watermarking location method. The time stepping is likewise utilized with the zero-information check convention and it can versatility oppose the delicate data spillage and implanting assaults, and is along these lines hearty to the cheating from the prover, verifier, or outsider. The encryption keys are additionally utilized with the information lattice technique and it can restrict the watermark, and make the watermark vigorous against assaults. In this proposed zero-information technique zero rate asset, timing and watermarking overhead can be accomplished. The proposed zero-information watermarking plan causes zero overhead. In this proposed information lattice technique signal-rich-workmanship code picture, can be portrayed. The proposed information network watermarking plan encodes the copyright confirmation data. The zero-information confirmation convention and information grid technique proposed in this paper is executed by MATLAB R2014a in which C programming language is utilized in it and ModelSim 10.5b in which VHDL coding is utilized in it, are running on a PC. The combination instrument Xilinx ISE 14.5 is likewise used to confirm and actualize the watermarking plan.

IMPLEMENTATION OF GRADIENT BASED ADAPTIVE INTERPOLATION ON FPGA

FPGA (Field Programmable Gate Array) structure can exploit the temporal and spatial parallelism of the system, subject to hardware constraints and processing mode of the system. Due to this property, real time image processing algorithms can implemented using this platform. Now a days High level Synthesis Tools (HLS) available. Which can used to configure FPGA. This paper presents a real time implementation of gradient-based adaptive interpolation using HLS. We received a speedup of 14X over general purpose processor.

Design of EMB-Based Moore FSMs

The complexity of algorithms implemented in digital systems grows. Methods are developed for most effective use of both hardware resources and energy. For engineers the problem of hardware resources optimization in design of control units is still an important issue. The standard way of implementing the control unit as a finite-state machine (FSM) is not satisfactory as it consumes considerable amounts of field-programmable gate arrays (FPGA) resources. This paper is devoted to the design of a Moore FSM in FPGA structure using look-up tables and embedded memory blocks (EMB) elements. The problem background is discussed. The method of the design of Moore FSM logic circuits with EMB based on splitting the set of logical conditions and the encoding of logical conditions is presented. Examples of design and research results are given.

Soft Processors as a Prospective Platform of the Future

Modern field-programmable gate arrays (FPGA) play a very important role in designing of new soft CPUs and integrated systems-on-chips. Compared to an application-specific integrated circuit (ASIC), FPGAs provide the highest degree of flexibility being almost fully application neutral. The price of such flexibility is higher usage of basic logic gates and decrease in circuit operating frequency caused by the use of switched interconnect fabric as opposed to fixed metal interconnect defined by masks at manufacturing for ASIC.However due to more regular and less complex FPGA structure they lead in terms of new IC manufacturing technologies adoption. Therefore we can expect next generation of general purpose FPGA devices based on 14nm norms in 2017.This article examines the applicability of Moore's Law to general purpose FPGAs, using datum for Xilinx Spartan and Altera Cyclone families. On the basis of the obtained data the conclusion that in the near future FPGAs become a prospective platform for general purpose CPUs implementation is drawn.

Implementing Double Error Correction Orthogonal Latin Squares Codes in SRAM-based FPGAs

This paper studies the implementation of Double Error Correction Orthogonal Latin Squares (OLS) in Xilinx Field Programmable Gate Arrays (FPGAs). Several existing options to implement the decoder are considered and evaluated. The results show that the decoder complexity can be significantly optimized by appropriately selecting the implementation that is better suited to the internal FPGA structure. A new implementation tailored for the FPGA structure is proposed, which has a more efficient physical resource utilization compared with the existing ones. It is shown that the improvement on resource utilization is also highly correlated with the soft error vulnerability. The proposed decoder scheme has a reduced soft error cross section compared with other implementations. Based on these results, it seems that optimizing the ECC implementation for FPGAs can be effective and may be useful for other codes.

Implementation of High Speed Operating FIR Filter with DA Algorithm Comparing Results with MAC Algorithm and Simple FIR Filter Result

Recent years there has been a increasing trend to implement digital signal processing functions in Field ProgrammableGate Array (FPGA). therefor, we need to put great effort in designing efficient architectures for digital signal processing functionssuch as FIR filters, which are widely used in audio and video signal processing, telecommunications etc. We are going to present amethod for implementing high speed Finite Impulse Response (FIR) filters using MAC (MULTIPLY AND ACCUMULATE) andDistributed Arithmetic (DA) method. MAC is a conventional FIR filter In these method adders, multipliers and delay elements areused. Distributed Arithmetic (DA) has been used to implement a bit-serial scheme of a general symmetric version of an FIR filter dueto its high stability and linearity by taking optimal advantage of the look-up table (LUT) based structure of FPGAs. The performanceof the DA technique for FIR filter design is analyzed and the results are compared to the MAC design technique.

Implementation of High Speed Operating FIR Filter with DA Algorithm Comparing Results with MAC Algorithm and Simple FIR Filter Result

Recent years there has been a increasing trend to implement digital signal processing functions in Field Programmable Gate Array (FPGA). therefor, we need to put great effort in designing efficient architectures for digital signal processing functions such as FIR filters, which are widely used in audio and video signal processing, telecommunications etc. We are going to present a method for implementing high speed Finite Impulse Response (FIR) filters using MAC (MULTIPLY AND ACCUMULATE) and Distributed Arithmetic (DA) method. MAC is a conventional FIR filter In these method adders, multipliers and delay elements are used. Distributed Arithmetic (DA) has been used to implement a bit-serial scheme of a general symmetric version of an FIR filter due to its high stability and linearity by taking optimal advantage of the look-up table (LUT) based structure of FPGAs. The performance of the DA technique for FIR filter design is analyzed and the results are compared to the MAC design technique.

A Novel Strategy of Area Cost Estimation for Custom Instruction Based on FPGA Architecture

Area cost estimation model is important for accurate measurement of area on reconfigurable processor. However, in the process of CI (Custom Instruction), traditional model can’t accurately estimate area cost of CI candidates. In the paper, we propose a novel strategy of area cost estimation. According to island-style FPGA (Field Programmable Gate Array) structure, the strategy firstly enumerated all BCs (Basic Cells) from data-path of CI candidates. Then checked all the validity of BCs enumerated, and selected the unique BC set to overlap original data-paths. We lastly used the effective estimation model based on BC to accurately measure area cost of candidates. Experimental results show that novel strategy can accurately estimate area cost of CI candidates, which is very close to actual result from a HLS (High Level Synthesis) tool, and deviation is less than 6%.

HIGH RESOLUTION TIME-INTERVAL MEASUREMENT SYSTEMS APPLIED TO FLOW MEASUREMENT

Abstract The designing process of high resolution time interval measurement systems creates many problems that need to be eliminated. The problems are: the latch error, the nonlinearity conversion, the different duty cycle coefficient of the clock signal, and the clock signal jitter. Factors listed above affect the result of measurement. The FPGA (Field Programmable Gate Array) structure also imposes some restrictions, especially when a tapped delay line is constructed. The article describes the high resolution time-to-digital converter, implemented in a FPGA structure, and the types of errors that appear there. The method of minimization and processing of data to reduce the influence of errors on the measurement is also described.

基于FPGA数据采集与共享的两种记录方式并存的电力系统录波器研制

两种录波方式并存的电力系统录波器综合了传统触发式录波和长过程录波两种记录方式，采用相互独立的记录系统。基于FPGA (Field Programmable Gate Array)数据采集与传输技术使得两个独立的录波系统共享交流采集回路。系统采用FPGA + DSP + POWERPC嵌入式硬件平台和VxWorks嵌入式实时操作系统。FPGA协调硬件系统工作时序，负责高速的数据采集和通讯，提供高速双口RAM；DSP负责数据运算及启动判断；POWERPC负责大容量高速数据存储。两种录波方式并存的电力系统录波器很好的满足了广东电网提出的故障录波技术规范。 The power system recorder with two recording ways integrates traditional trigger fault recorder for transient signal and recorder for continuous signal. The two recorder system is entirely independent; it shares sampling data by the sampling and transmitting based FPGA (Field Programmable Gate Array). Hardware system bases structure of FPGA + DSP + POWERPC. Software bases VxWorks. FPGA coordinates hardware system timing control and takes in charge of sampling and communication and provide dualport RAM. DSP takes in charge of calculation. POWERPC take in charge of store data. The power system recorder with two recording ways meets Guangdong Power technical specification.

Hologram synthesis accelerated in field programmable gate array by partial quadratic interpolation

Numerical models of holograms are available but their evaluation is a very computationally intensive task. We present an acceleration algorithm for optical field synthesis suitable for the reduced occlusion method of hologram synthesis. The acceleration uses an approximation that is designed for a field programmable gate array (FPGA) and therefore it mostly uses fixed point numbers. The work describes the approximation, its fixed-point modification, and the resulting FPGA structure. The results presented show that the solution produces high-quality holograms in a significantly reduced time due to efficient FPGA implementation.

FPGA ACCELERATION FOR DNA SEQUENCE ALIGNMENT

In this paper, we present two new hardware architectures that implement the Smith–Waterman algorithm for DNA sequence alignment. Previous low-cost approaches based on Field Programmable Gate Array (FPGA) technology are reviewed in detail and then improved with the goal of increased performance at the same cost (i.e., area). This goal is achieved through low level optimizations aimed to adapt the systolic structure implementing the algorithm to the regular structure of FPGAs, essentially finding the optimum granularity of the systolic cells. The proposed architectures achieve processing rates close to 1 Gbps, clearly outperforming previous approaches. Comparing to the reported FPGA results of the computation of the edit-distance between two DNA sequences, throughput is doubled for the same clock frequency with a minimum area penalty. The design has been implemented on an FPGA-based prototyping board integrated into a bioinformatics system. This has allowed validating the approach in a real system (i.e., including I/O and database access), and comparing the proposed hardware solution to purely software approaches. As shown in the paper, the results are outstanding even for slow-rate buses.

CeRA: a router for symmetrical FPGAs based on exact routing density evaluation

We present a new performance and routability driven routing algorithm for symmetrical array-based field-programmable gate arrays (FPGAs). A key contribution of our work is the overcoming of one essential limitation of the previous routing algorithms: inaccurate estimations of routing density that were too general for symmetrical FPGAs. To this end, we formulate an exact routing density calculation that is based on a precise analysis of the structure (switch block) of symmetrical FPGAs and utilize it consistently in global and detailed routings. With an introduction to the proposed accurate routing metrics, we describe a new routing algorithm, called cost-effective net-decomposition-based routing, which is fast and yet produces remarkable routing results in terms of both routability and net/path delays. We performed extensive experiments to show the effectiveness of our algorithm based on the proposed cost metrics.

An optimized architecture for a rapid-prototype-emulator

An ASIC prototype based on field programmable gate-arrays (FPGA) is a fast and cheap alternative to a silicon based prototype for design verification. To meet the high performance and complex functionality of the digital part of ASICs, it is necessary to connect FPGAs to an array. The connection-structure determines the realtime ability and the variety of designs that can be implemented into the FPGA-array. A new architecture for the connection structure of FPGAs as the base for a rapid-prototype emulation-system is presented. This architecture leads in relation to conventional systems to be a better usage of the FPGAs and to an emulation-limiting close to realtime in most designs.