Field-programmable Gate Arrays Look-up Tables Research Articles

Optimizing FPGA Logic Circuitry for Variable Voltage Supplies

Unlike central processing units (CPUs), field-programmable gate arrays (FPGAs) have conventionally been powered with a fixed supply voltage ( $V_{\text {dd}}$ ). However, recent efforts have shown that adopting dynamic voltage scaling reduces FPGA power consumption significantly. In this article, we analyze the delay sensitivity of different FPGA circuit elements to supply voltage changes and determine that conventional lookup table (LUT) designs greatly impact variable ${V_{\text {dd}}}$ operation. To build FPGAs with lower delay sensitivity to ${V_{\text {dd}}}$ , we propose several new LUT designs, including gate boosting the LUT, decoding the slowest two inputs of the LUT, and using separate voltage islands for the FPGA LUTs and routing. Our fastest proposed design (decode-driver island) reduces the area-delay product of the FPGA logic plus routing tile compared to a conventional design by 12% and 52% at ${V_{\text {dd}}}$ values of 0.8 V (the nominal voltage) and 0.6 V, respectively. Since our proposed FPGA tile designs are faster and have lower delay sensitivity to voltage, they offer better ${\text {Energy-Delay} {{^{\mathrm{ 2}}}}}$ product ( ${\text {ED} {{^{\mathrm{ 2}}}}}$ ) than that of the baseline at nominal ${V_{\text {dd}}}$ and below. Our decode-driver-island FPGA achieves a 26% ${\text {ED} {{^{\mathrm{ 2}}}}}$ reduction over the conventional design at the most efficient ${\text {ED} {{^{\mathrm{ 2}}}}}$ operating point.

A mechanism for detecting on-chip radio frequency interference of field-programmable gate array

One-chip measurements without modifying the physical structure of packaged integrated circuits such as field-programmable gate arrays (FPGA) is challenging. This paper proposes a sensor for detecting the radio frequency interference (RFI) on the supply inside the FPGA chip. The core of the sensor is a ring oscillator built with FPGA look-up tables. The paper proposes a model to predict the response of the ring oscillator to power supply RFI, and shows that the normalized frequency shift of the ring oscillator resulting from the interference is determined by the amplitude of the interference. This relationship is independent of the interference frequency and the size of the ring oscillator. To verify the model, simulations on transistor-level look-up tables of 130-nm and 40-nm technologies were performed. The simulation results matched well with the model. In addition to simulation, an FPGA test board was fabricated. Measurements of FPGA RFI response were performed and the results were consistent with the theoretical model. The effect of the interference on the ring oscillator provided a mechanism to detect the amplitude of the supply interference on the FPGA chip. The frequency of the ring oscillator was monitored through the supply pin by measuring the spectrum of the supply noise. The properties of the sensor, such as constant response in a wide frequency range, insensitiveness to the oscillator size, ease of implementation, and minimal modification requirement of the physical structure, made it suitable for performing on-chip FPGA measurements.

Characteristic features of LUT setting codes of Intel FPGAs

State-of-the-art digital circuit design widely uses field programmable gate arrays (FPGAs), in which the functions of logic cells and their connections are set up. That is defined in the configuration file that is loaded in the configuration memory cells (static random access memory) of FPGA from external memory. The logic itself is implemented in the so-called LUTs (Look Up Tables), multiplexors that implement memory cells, are based on transmitting transistors and represents a tree that is activated by a specific variable collection. The setting is multiplexor data, therefore logical (switching) function values for the specific collection are transmitted to the tree output. As it turns out, the associated LUT setting code can be decoded and used for analyzing synthesis results in Quartus II by Altera that has been acquired by Intel. Now Intel also specializes in FPGA production. The article considers an example of the synthesis of a simple combinational finite state machine that implements the so-called majority function (2 out of 3). This function equals 1 if the majority of variables equals 1. Majority function implementation diagram is synthesized in Quartus II that builds a special BDF (Block Diagram/Schematic File) file. The resulting diagram is examined with Map Viewer. In the appropriate diagram, LUT (Logic Cell Comb) setting codes for implementation of the specified function are set forth in the form of four-digit hexacodes. Decoding is shown for setting codes for logic cells of FPGA LUT type that describe the content of the respective truth tables of functions that depend on the input variable machine. The article shows the code changes in the process of diagram optimization by Quartus II with possible modification of the variables sequence order and correspondence with the inputs of a four-input LUT without modifications to the logical function. If Stratix IIGX FPGA is used that has the so-called adaptive logic modules (ALM) with 6 inputs, Quartus II uses 64-bit codes (eight-digit hexacodes). Respective coding is also examined in this paper.

A Custom FPGA Processor for Physical Model Ordinary Differential Equation Solving

Models of physical systems, such as of human physiology or of chemical reactions, are typically comprised of numerous ordinary differential equations (ODEs). Today's designers commonly consider simulating physical models utilizing field-programmable gate arrays (FPGAs). This letter introduces a resource efficient custom processor-the differential equation processing element, or DEPE-specifically designed for efficient solution of ODEs on FPGAs, and also introduces its accompanying compilation tools. We show that a single DEPE on a Xilinx Virtex6 130T FPGA executes several physiological models faster than real-time while requiring only a few hundred FPGA lookup tables (LUTs). Experiments with a commercial high-level synthesis(HLS) tool show that while a single DEPE is 5-50× slower than HLS circuits, DEPE is 10-200 × smaller. We show that a single DEPE is only 10× slower than a relatively massive and costly 3 GHz Pentium 4 desktop processor for ODE solving, and its speed is also competitive with a 700 Mhz TI digital signal processor and an 450 Mhz ARM9 processor. DEPE is 4×-17× faster than a Xilinx MicroBlaze soft-core processor and 3 ×-6 × smaller. DEPE thus represents an excellent processing element for use by itself for small physical models, and in future parallel networks for larger models.

Errata to “Identification and Classification of Single-Event Upsets in the Configuration Memory of SRAM-Based FPGAs”

This paper presents the radiation testing of a commercial-off-the-shelf SRAM-based field-programmable gate arrays (FPGAs) with heavy ions. Test experiments have been conducted to identify and to classify the single-event upsets (SEUs) in the configuration memory that induce single-event functional interrupt for the user-implemented circuit. Moreover the paper presents a new approach for assessing the effects of SEUs based on the combination of radiation testing and simulation-based fault injection tool. First experimental results show the FPGA look-up table (LUT) resources (used to implement combinatorial logic) are the most sensitive to SEUs, whereas interconnect resources are the most critical for the device cross section because they use the largest number of configuration bits. The analysis of experimental data underlines that the most probable error affecting interconnections is the shorting of two nets. This observation indicates that new fault models should be considered along with the classic stuck-at one model designing fault-tolerant architectures, which are intended for implementation in FPGA devices.

Identification and classification of single-event upsets in the configuration memory of SRAM-based FPGAs

This paper presents the radiation testing of a commercial-off-the-shelf SRAM-based field-programmable gate arrays (FPGAs) with heavy ions. Test experiments have been conducted to identify and to classify the single-event upsets (SEUs) in the configuration memory that induce single-event functional interrupt for the user-implemented circuit. Moreover the paper presents a new approach for assessing the effects of SEUs based on the combination of radiation testing and simulation-based fault injection tool. First experimental results show the FPGA look-up table (LUT) resources (used to implement combinatorial logic) are the most sensitive to SEUs, whereas interconnect resources are the most critical for the device cross section because they use the largest number of configuration bits. The analysis of experimental data underlines that the most probable error affecting interconnections is the shorting of two nets. This observation indicates that new fault models should be considered along with the classic stuck-at one model designing fault-tolerant architectures, which are intended for implementation in FPGA devices.