Field Programmable Gate Array Development Research Articles

FPGA-Based Vit Inference Accelerator Optimization

In the AI era, the emergence of the transformer model contributes to a significant shift in the natural language processing field. Its derivative, the Vision Transformer (ViT), adapts these principles for image recognition and demonstrates superior performance over traditional Convolutional Neural Networks (CNNs). Despite its excellent performance, deploying these models on edge devices is impeded by their extensive computational demands and large memory requirements, which poses challenges for the limited resources and real-time processing needs at the edge. Hence, it is necessary to develop a new hardware accelerator to optimize ViT architecture. This paper reviews the development of Field-Programmable Gate Array (FPGA)-based ViT inference accelerators, focusing on their architectures and applications in solving the dilemmas of ViT model deployment. Additionally, it explores the optimization approaches on both algorithm and hardware and traces the advancements in deploying AI models at the edge using FPGAs. It summarizes the current trends in research on FPGA-based ViT accelerators and provides insights into future directions for innovations in hardware-accelerated AI. Generally, by tracing the related works for FPGA-based ViT inference accelerator optimization, this article presents a useful snapshot of current research in ViT hardware accelerators and contributes to clarifying future research directions in this area.

Design and development of FPGA based trigger system for automation of metallic tokamak (MT-I)

A field-programmable gate array (FPGA)-based trigger system (FTS) is designed and developed to replace the existing microcontroller-based system for the automation of metallic tokamak (MT-I). MT-I consists of three main systems: MT-I vacuum vessel and gas filling system, a pulsed power supply system, an electronic system based on diagnostics and data acquisition (DAQ) systems. The power supply system provides pulsed power input to the central solenoid (CS), poloidal field coils (PF), toroidal field coils (TF), and microwave systems using thyristors and insulated-gate bipolar transistors (IGBTs). The (DAQ) system acquires experimental data from MT-I diagnostics using national instruments (NI) DAQ cards. A concurrent processing system is required to incorporate time delay in the triggering process of central solenoid (CS), poloidal field coils (PF), toroidal field coils (TF), microwave source and DAQ systems. Therefore, an FTS is designed and developed to complement the processing capability, unlike a microcontroller. The FTS has twenty concurrent triggering channels, adjustable from time reference zero, and control from a simple graphical user interface (GUI) designed on LabVIEW. For current buffering and optical isolation against high voltages in the MT-I power supply system, a peripheral electronic system (PES) and field trigger modules (FTM) have been developed as part of FTS. The designed and developed FTS was tested successfully on MT-I.

Ensuring cybersecurity of FPGA as a service with the use of penetration testing of components

The subject of study in this article is modern penetration testing technologies, in which the test object is the implementation of a service based on a platform using Field Programmable Gate Array (FPGA) resources. The goal of this study is to improve modern methods of penetration testing of services provided by FPGA as a Service (FaaS) to find vulnerabilities for further fixing and increasing the level of services security and trust. Task: to analyze the technological capabilities for the development of FPGA as a Service; to analyze possible threats for FPGA as a Service platform; to analyze the structure of the FPGA as a Service platform and the peculiarities of attacks on it; to analyze options for using the penetration testing standard; to propose the classification of possible use of FPGA as a Service platform for solving of cybersecurity tasks; and to propose the sequence of critical components of ensuring of the cybersecurity of FPGA as a Service platform. The following results were obtained based on the tasks. The analysis of the capabilities of existing chips, FPGA accelerator cards, programming technologies, and the integrated environments of a leading company for creation of FPGA as a Service is performed. A study on the cybersecurity problems of FPGA as a Service platforms is conducted, and a set of components to ensure the cybersecurity of FPGA as a Service Platform is proposed. Modern cybersecurity threats of FPGA as a Service platforms are analyzed. A threat structure for FPGA as a Service is proposed. The possibility of applying a penetration testing standard to FPGA services is considered. Regular audits and penetration testing are crucial elements of a cybersecurity strategy and help maintain customer and user trust in FPGA services. Based on the analysis of the possible use of FPGA as a Service to solve cybersecurity tasks, a classification of five variants considering FPGA as an object and tool is proposed. The sequence of critical components of ensuring of the cybersecurity of FPGA as a Service platform is proposed to correspond to modern known threats. Complex activities, including the software updates, security monitoring, auditing, and penetration testing, based on security standards. Conclusions. The primary contribution and scientific novelty of the obtained results is the research into the possibilities of penetration testing for services, where the test object is a platform with access to FPGA. As in many other areas, ensuring the cybersecurity of FPGA as a Service platform is complex, and ignoring any component can lead to critical consequences. Applying only penetration testing is not enough; therefore, a comprehensive list of cybersecurity measures for FPGA as a Service platforms is provided, underlining the urgency and necessity of their implementation.

Exploring the significance and applications of Field Programmable Gate Arrays in modern integrated circuits

In recent years, the rapid advancement of electronic technology and large-scale integrated circuit technology has led to increased integration of integrated circuits and expanding system scales on integrated motherboards. This evolution presents new challenges and demands in system design. Field Programmable Gate Arrays (FPGAs), a vital VLSI technology, have found extensive applications in communication, image processing, computers, and other domains, becoming a pivotal component of contemporary electronic systems. This paper aims to enhance the understanding of FPGAs by first delving into their theoretical foundations, followed by an overview of their general structural elements and a historical perspective on FPGA development. Additionally, this analyse and summarize relevant literature in the third section, focusing on the three primary application areas of FPGAs, elucidating their research processes and findings. Finally, the fourth section offers insights into the future directions of FPGA development, grounded in the current context. By acquainting readers with FPGAs essential attributes and its multifaceted applications, this paper underscores the pivotal role of FPGAs in the landscape of modern integrated circuits.

Designing hardware for a robust high-speed cryptographic key generator based on multiple chaotic systems and its FPGA implementation for real-time video encryption

Recent advancements in communication technologies have highlighted the pivotal role of information security for all individuals and entities. In response, researchers are increasingly focusing on cryptographic solutions to ensure the reliability of confidential information. Recognizing the superiority of chaotic systems preference as entropy source of cryptographic systems, this paper proposes a novel true random number generator (TRNG) design by combining four different chaotic systems outputs, tailored for real-time video encryption application. These chaotic systems are continuous-time Lorenz and fractional-order Chen-Lee systems, as well as discrete-time Logistic and Tent maps. This study generates true random bit (TRB) sequences at a high bit rate (25 Mbps) through the hardware implementations of four distinct chaotic systems to have the best statistical randomness in the resulting output. Then, the cryptographic true random key bits (8-bit at 25 MHz frequency) are employed in the post-processing with real-time video data by using the XOR operation, a fundamental post-processing algorithm. The real-time video encryption application is executed on an experimental assembly, composed of a Field Programmable Gate Array (FPGA) development kit, an OV7670 camera module, a VGA monitor, and prototype circuit boards for the chaotic systems. To evaluate the effectiveness of the proposed encryption system, several security assessments are conducted. These include NIST SP 800 − 22 statistical tests, FIPS 140-1 standards, chi-square tests, histogram and correlation analysis, and NPCR and UACI differential attack resilience tests. Consequently, the findings suggest that the presented real-time embedded cryptosystem is robust and suitable for secure communications, particularly in the realm of video transmission.

System for the fast readout and tests of pixel IC operating in single photon counting mode using PCIe-based FPGA

Hybrid Pixel Detectors (HPDs) have become popular in particle and photon detection techniques in recent years. This type of devices consists of two parts: a pixelated sensor (based on Si, Ge, GaAs, CZT, etc.), and a readout Integrated Circuit (IC), which usually contains thousands of pixels and millions of transistors. ICs suffer from the inaccuracies of manufacturing processes, therefore HPDs have to be thoroughly tested before the sensor bump-bonding process. This paper presents a highly efficient system for the automated testing of pixelated HPDs. The presented solution is based on the Intel Arria 10 GX Field Programmable Gate Array (FPGA) development kit and a Linux-powered Personal Computer (PC), connected via Peripheral Component Interconnect Express (PCIe) 8x Gen. 3 interface. The proposed system has been built of well-thought-out modules connected through the set of precisely defined interconnects. This approach enabled the development of an architecture that may be easily implemented in both PCIe-based systems and System-on-Chip devices, such as Intel Agilex SoC. The presented system has been tested with both a manufactured IC and a model implemented in the FPGA.

MBIST Implementation and Evaluation in FPGA Based on Low-Complexity March Algorithms

March algorithms are widely used in Memory Built-In Self-Test (MBIST) on-chip memory testing, providing linear test complexities that reduce the test time and cost. However, studies show that March algorithms with complexities lower than 18N have poor coverages of faults that have emerged with the advent of the nanometer process technologies and are more relevant to nowadays memories. New March AZ1 and March AZ2 algorithms, with 13N and 14N complexities, respectively, were introduced to provide optimum coverage of those faults and to produce a shorter test than an 18N-complexity test algorithm with a lesser area overhead, thus reducing chip manufacturing costs. This paper presents the implementation and validation of MBIST controllers that applied the March AZ1 and March AZ2 algorithms in a Field-Programmable Gate Array (FPGA) device. They were implemented in the Intel Max 10 DE10-Lite FPGA Development Board. A test generator was built in FPGA, as an alternative to the external tester, to provide test vectors required in initiating the test on the memory model using the implemented MBIST. The FPGA experimental tests demonstrated that they function correctly as the expected test sequences were observed. In addition, their fault detection abilities were also validated through tests on a fault-injected memory model, which shows that the implemented March AZ1 and March AZ2 provide 80.6% and 83.3% coverage of the intended faults, respectively, which outperform any other existing 14N-complexity March algorithms.

Design and Testing of a Wireless Communication Enabled FPGA Development Board: A Comprehensive Education and Application Platform from IoT to Circuit Design

Field Programmable Gate Array (FPGA) is an integrated circuit (IC) that can be reprogrammed or configured by the customer or designer after production for rapid prototyping and post-process development. In this study, a cost-effective FPGA development board is designed to create basic engineering education applications and implement them in real-time. The FPGA development board utilizes an Altera Cyclone IV E-series chip and includes Bluetooth and Wi-Fi modules to provide a wider range of applications. This integration simplifies the use of wireless communication in various projects and applications for researchers and engineers. To verify the accuracy of the proposed board, simulations of selected digital designs and Bluetooth applications were first performed in VHDL (Very High Speed Integrated Circuit Hardware Description Language) using Intel® Quartus® Prime Lite Edition software. Then, experiments were performed on the board following the pin assignment configurations. It was observed that the developed applications worked successfully on the FPGA development board. As a result, this board, equipped with Bluetooth and Wi-Fi modules, offers a fast and cost-effective solution for users in various fields such as mobile, robotics, smart home systems, and remote monitoring and control devices

A Field Programmable Gate Array Placement Methodology for Netlist-Level Circuits with GPU Acceleration

Field Programmable Gate Arrays (FPGAs), renowned for their reconfigurable nature, offer unmatched flexibility and cost-effectiveness in engineering experimentation. They stand as the quintessential platform for hardware acceleration and prototype validation. With the increasing ubiquity of FPGA chips and the escalating scale of system designs, the significance of their accompanying Electronic Design Automation (EDA) tools has never been more pronounced. The placement process, serving as the linchpin in FPGA EDA, directly influences FPGA development and operational efficiency. This paper introduces an FPGA placement methodology hinging on the Verilog-to-Routing (VTR) framework. We introduce a novel packing approach grounded in the weighted Edmonds’ Blossom algorithm, ensuring that the CLB generation strategy aligns more closely with load-balanced distribution. Furthermore, we enhanced the electric field-driven resolver placement process for CLB locations and leverage GPU-accelerated design. Experimental results demonstrate substantial improvements over the traditional VTR algorithm, with an average optimization of 28.42% in the packing process runtime, an average acceleration ratio of 2.85 times in the placement phase, and a 39.97% reduction in total packing and placement runtime consumption.

FPGA: The super chip in the age of artificial intelligence

In modern society, artificial intelligence (AI) is developing more rapidly. And the Field Programmable Gate Array (FPGA) has always been the focus of research as a driving platform. This paper studies in detail the theoretical basis, applications, defects, and future development directions of FPGAs. It is concluded that FPGA has three characteristics: gate array, programmable, and scene, and the detailed positioning of FPGA, the structure, principle, tools, process, and description language of FPGA design. And the unique advantages of FPGA in the field of artificial intelligence: flexible and configurable, special optimizations for convolutional neural networks, and deterministic low latency. Several typical applications of FPGA in the field of artificial intelligence, deficiencies and solutions, and two future development directions. This article will make a great contribution to the development of FPGA in the field of artificial intelligence in the future.

FPGA based telecommand system for balloon-borne scientific payloads

Abstract Telecommand (TC) plays a crucial role in the success of high-altitude balloon experiments. Bose, Ray-Chaudhuri, Hocquenghem (BCH) codes are commonly employed to ensure reliable command operation. The Balloon Facility (BF) of Tata Institute of Fundamental Research (TIFR) uses a TC system based on BCH (31,16) coding technique, to control balloon and payload operations. This paper presents prototyping and implementation of TC encoder and decoder using Spartan 6 Field Programmable Gate Array (FPGA). The code is written in Very high-speed integrated circuit Hardware Description Language (VHDL). Simulation and synthesis are done using Xilinx ISE 14.7 design suite. Simulation results show the design is robust. The TC encoder is implemented in a commercial FPGA development board and the TC decoder is implemented in a specially designed FPGA board, successfully. This paper presents the salient features of the TC system in use and the implementation of the system using FPGA.

Measurement of Ultrasound Propagation Velocity in Liquids Using an FPGA Module

The design and development of an ultrasonic device for the measurement of ultrasonic propagation velocity in liquids based on Field Programmable Gate Array (FPGA) architecture is described. The device was implemented using a DE0-Nano-SoC Development Kit FPGA development module, a 2x16 LCD Display, a 2-channel quadrature output optical encoder with push button, two ultrasonic transducers and an external module for interfacing with the transducers containing the circuits corresponding to the transmitter, receiver and amplifier. For the development, the Altera Integrated Development Environment (IDE) software called Quartus II was used, which allows the logical design and supports different HDL hardware description languages, such as Verilog and VHLD. Although the device was calibrated to measure the acoustic velocity of water in the range of 35°C to 40°C, due to its design characteristics it is feasible to extend its application to measure acoustic velocity in different liquids, delimiting the operation intervals. The device acquires 100 readings per second, calculates the average with polynomial adjustment and displays the value of the ultrasonic propagation velocity in the fluid with a resolution of 0.01 [m/s] with a refresh rate of one second.

Ethernet Packet to USB Data Transfer Bridge ASIC with Modbus Transmission Control Protocol Based on FPGA Development Kit

This paper proposes an Ethernet packet transformation and transmission architecture between Modbus transmission control protocol (Modbus TCP) and universal serial bus (USB) 3.0 developed with a field-programmable gate array (FPGA) development kit. The proposed architecture is used to complete packet transformation and transmission between Ethernet and USB 3.0 for application in induction motor (IM) control. The Ethernet receiver receives and analyses Modbus TCP packets and sends the source address, destination address, IP header, and Modbus TCP header to the register to verify the correctness of the packet. The Modbus TCP packet is stored in static random access memory and awaits access through a USB 3.0 module. An FPGA development kit (Intel DE10-Standard) is used for functional verification. The measured results show that the latency, throughput, and dynamic power are 18.845 μs, 950.31 Mbps, and 142.17 mW, respectively, at a voltage of 1.8 V and an operating frequency of 125 MHz. The main advantage is that the proposed Ethernet and USB bridge performs high throughput and short latency with FPGA development kit and that an application specific integrated circuit (ASIC) is provided with low power consumption. The robustness and convenience of the proposed ASIC are especially advantageous. The motivation is to resolve an existing problem that Ethernet and USB operate on different platforms.

FPGA Synthesis of Ternary Memristor-CMOS Decoders for Active Matrix Microdisplays

The search for a compatible application of memristor-CMOS logic gates has remained elusive, as the data density benefits are offset by slow switching speeds and resistive dissipation. Active microdisplays typically prioritize pixel density (and therefore resolution) over that of speed, where the most widely used refresh rates fall between 25–240 Hz. Therefore, memristor-CMOS logic is a promising fit for peripheral I/O logic in active matrix displays. In this paper, we design and implement a ternary 1–3 line decoder and a ternary 2–9 line decoder which are used to program a seven segment LED display. SPICE simulations are conducted in a 50-nm process, and the decoders are synthesized on an Altera Cyclone IV field-programmable gate array (FPGA) development board which implements a ternary memristor model designed in Quartus II. Our approach to logic synthesis demonstrates a potential way forward for simulating large-scale memristor-CMOS circuits without embedded RRAM for functional verification, and our SPICE results show an improvement in data density of a variety of decoders by a factor between 3.6-8.5. While the switching speed of memristors are one of several bottlenecks to using them in combinational logic, the comparatively slow refresh rates of typical microdisplays indicate this to be a tolerable trade-off, which promotes data density over speed.

Field programmable gate arrays implementation of different standard deviation estimation techniques

Additive white Gaussian noise level estimation has found its application in many fields such as biomedical signal processing, communication system, and image processing. Many methods have been proposed with different output accuracy, system complexity, power consumption, and speed. In this paper, three of the most well-known and largely used algorithms (median based, root mean square (RMS) based, and P84 based methods) have been implemented and investigated in a full comparison between them to find their advantage and disadvantage, and the suitability of each method for a specific application. The three designs are created using Xilinx system generator (XSG) and implemented on Xilinx field programmable gate arrays (FPGA) development board with Zynq series "XC7Z020-1CLG484", to evaluate the design's performance and the results are discussed in the paper.

Re-configurable, expandable, and cost-effective heterogeneous FPGA cluster approach for resource-constrained data analysis

Field programmable gate arrays (FPGAs) have become widely prevalent in recent years as a great alternative to application-specific integrated circuits (ASIC) and as a potentially cheap alternative to expensive graphics processing units (GPUs). Introduced as a prototyping solution for ASIC, FPGAs are now widely popular in applications such as artificial intelligence (AI) and machine learning (ML) models that require processing data rapidly. As a relatively low-cost option to GPUs, FPGAs have the advantage of being reprogrammed to be used in almost any data-driven application. In this work, we propose an easily scalable and cost-effective cluster-based co-processing system using FPGAs for ML and AI applications that is easily reconfigured to the requirements of each user application. The aim is to introduce a clustering system of FPGA boards to improve the efficiency of the training component of machine learning algorithms. Our proposed configuration provides an opportunity to utilise relatively inexpensive FPGA development boards to produce a cluster without expert knowledge in VHDL, Verilog, or the system designs related to FPGA development. Consisting of two parts – a computer-based host application to control the cluster and an FPGA cluster connected through a high-speed Ethernet switch, allows the users to customise and adapt the system without much effort. The methods proposed in this paper provide the ability to utilise any FPGA board with an Ethernet port to be used as a part of the cluster and unboundedly scaled. To demonstrate the effectiveness of the proposed work, a two-part experiment to demonstrate the flexibility and portability of the proposed work – a homogeneous and heterogeneous cluster, was conducted with results compared against a desktop computer and combinations of FPGAs in two clusters. Data sets ranging from 60,000 to 14 million, including stroke prediction and covid-19, were used in conducting the experiments. Results suggest that the proposed system in this work performs close to 70% faster than a traditional computer with similar accuracy rates.

Design and Performance Analysis of X-ray Photoelectric Collector for Logistics Transportation

The strong conveyor belt has been widely used in mines, ports, wharves, power plants, steel mills, and other fields. It is one of the main transportation equipment in modern production. In coal mine production, the logistics conveyor belt is essential equipment. The increased load can scratch and age the conveyor belt. Then, coupled with the elongation of joints, the equipment fails. This work designs an X-ray Photoelectric (XP) collector for logistics transportation and puts forward the design scheme. This work expounds on the hardware circuit of the XP collector, mainly based on the Image Capture Card (ICC) of the S8865 module and the serial/parallel data acquisition board based on the AD7667 chip. In the test, the Field Programmable Gate Array (FPGA) development tool ISE of Xilinx company is used to design the software of the XP collector to collect logistics X-ray signals. The oscilloscope analyzes the ICC control signal RESET, which repeatedly appears in a certain period. The S8865 module is controlled to collect X-ray signals continuously; the analog output signal of the S8865 module is observed. Under the control of a 1 MHz clock, the S8865 module outputs a stable analog signal. Similarly, observing the differential signal output of the differential processing circuit on the ICC through the oscilloscope finds that the differential signal is consistent with the original signal. Further positive input/output of the signal conditioning circuit of the serial/parallel data acquisition board is observed after the differential signal is switched. The single-ended signal after switching is consistent with the differential signal’s positive input signal.

FPGA Implementation for the Sigmoid with Piecewise Linear Fitting Method Based on Curvature Analysis

The sigmoid activation function is popular in neural networks, but its complexity limits the hardware implementation and speed. In this paper, we use curvature values to divide the sigmoid function into different segments and employ the least squares method to solve the expressions of the piecewise linear fitting function in each segment. We then adopt an optimization method with maximum absolute errors and average absolute errors to select an appropriate function expression with a specified number of segments. Finally, we implement the sigmoid function on the field-programmable gate array (FPGA) development platform and apply parallel operations of arithmetic (multiplying and adding) and range selection at the same time. The FPGA implementation results show that the clock frequency of our design is up to 208.3 MHz, while the end-to-end latency is just 9.6 ns. Our piecewise linear fitting method based on curvature analysis (PWLC) achieves recognition accuracy on the MNIST dataset of 97.51% with a deep neural network (DNN) and 98.65% with a convolutional neural network (CNN). Experimental results demonstrate that our FPGA design of sigmoid function can obtain the lowest latency, reduce absolute errors, and achieve high recognition accuracies, while the hardware cost is acceptable in practical applications.

Automatic RTL Generation Tool of FPGAs for DNNs

With the increasing use of multi-purpose artificial intelligence of things (AIOT) devices, embedded field-programmable gate arrays (FPGA) represent excellent platforms for deep neural network (DNN) acceleration on edge devices. FPGAs possess the advantages of low latency and high energy efficiency, but the scarcity of FPGA development resources challenges the deployment of DNN-based edge devices. Register-transfer level programming, hardware verification, and precise resource allocation are needed to build a high-performance FPGA accelerator for DNNs. These tasks present a challenge and are time consuming for even experienced hardware developers. Therefore, we propose an automated, collaborative design process employing an automatic design space exploration tool; an automatic DNN engine enables the tool to reshape and parse a DNN model from software to hardware. We also introduce a long short-term memory (LSTM)-based model to predict performance and generate a DNN model that suits the developer requirements automatically. We demonstrate our design scheme with three FPGAs: a zcu104, a zcu102, and a Cyclone V SoC (system on chip). The results show that our hardware-based edge accelerator exhibits superior throughput compared with the most advanced edge graphics processing unit.

MLoF: Machine Learning Accelerators for the Low-Cost FPGA Platforms

In Internet of Things (IoT) scenarios, it is challenging to deploy Machine Learning (ML) algorithms on low-cost Field Programmable Gate Arrays (FPGAs) in a real-time, cost-efficient, and high-performance way. This paper introduces Machine Learning on FPGA (MLoF), a series of ML IP cores implemented on the low-cost FPGA platforms, aiming at helping more IoT developers to achieve comprehensive performance in various tasks. With Verilog, we deploy and accelerate Artificial Neural Networks (ANNs), Decision Trees (DTs), K-Nearest Neighbors (k-NNs), and Support Vector Machines (SVMs) on 10 different FPGA development boards from seven producers. Additionally, we analyze and evaluate our design with six datasets, and compare the best-performing FPGAs with traditional SoC-based systems including NVIDIA Jetson Nano, Raspberry Pi 3B+, and STM32L476 Nucle. The results show that Lattice’s ICE40UP5 achieves the best overall performance with low power consumption, on which MLoF averagely reduces power by 891% and increases performance by 9 times. Moreover, its cost, power, Latency Production (CPLP) outperforms SoC-based systems by 25 times, which demonstrates the significance of MLoF in endpoint deployment of ML algorithms. Furthermore, we make all of the code open-source in order to promote future research.