Field Programmable Gate Array Architecture Research Articles

"Enhanced DA Algorithm for FIR Filter Design and FPGA Implementation"

Abstract: This study looks into the difficulties of using the Distributed Arithmetic (DA) method for Finite Impulse Response (FIR) filters on Field-Programmable Gate Arrays (FPGAs). It focuses on how coefficients are represented, balancing precision using fixed-point arithmetic and quantization. The research explores ways to optimize memory use, aiming to store data more efficiently within FPGA resources and reduce memory needs. To speed up computations, it examines how to make accessing lookup tables faster and suggests improvements in design. The study also considers how to manage FPGA resources effectively, balancing latency, throughput, and resource use. It looks at specific improvements to the DA method for FIR filters to make better use of resources and enhance performance. Overall, this work provides insights and solutions for algorithm design, memory use, lookup table speed, and FPGA architecture to make DA-based FIR filter implementations on FPGAs more efficient.

A FPGA Accelerator of Distributed A3C Algorithm with Optimal Resource Deployment

The asynchronous advantage actor-critic (A3C) algorithm is widely regarded as one of the most effective and powerful algorithms among various deep reinforcement learning algorithms. However, the distributed and asynchronous nature of the A3C algorithm brings increased algorithm complexity and computational requirements, which not only leads to an increased training cost but also amplifies the difficulty of deploying the algorithm on resource-limited field programmable gate array (FPGA) platforms. In addition, the resource wastage problem caused by the distributed training characteristics of A3C algorithms and the resource allocation problem affected by the imbalance between the computational amount of inference and training need to be carefully considered when designing accelerators. In this paper, we introduce a deployment strategy designed for distributed algorithms aimed at enhancing the resource utilization of hardware devices. Subsequently, a FPGA architecture is constructed specifically for accelerating the inference and training processes of the A3C algorithm. The experimental results show that our proposed deployment strategy reduces resource consumption by 62.5% and decreases the number of agents waiting for training by 32.2%, and the proposed A3C accelerator achieves 1.83× and 2.39× improvements in speedup compared to CPU (Intel i9-13900K) and GPU (NVIDIA RTX 4090) with less power consumption respectively. Furthermore, our design shows superior resource efficiency compared to existing works.

Recent advances on reliability of FPGAs in a radiation environment

In recent years, SRAM-based Field-Programmable Gate Arrays (FPGAs) have seen a surge in deployment within aerospace applications. Despite their widespread use, these FPGAs, particularly their embedded Static Random Access Memory (SRAM) and user logic, exhibit a notable susceptibility to Single Event Upsets (SEU), a phenomenon leading to erroneous connections or routing discrepancies. This paper presents an exhaustive survey of fault-tolerance methodologies pertinent to SRAM-based FPGAs operating in radiation-intensive environments. Initially, we delineate the architecture of the SRAM-based FPGAs, elucidating the mechanisms underlying SEU occurrences and their subsequent malfunctions. This is followed by a detailed exploration of various strategies employed to assess the resilience of SRAM-based FPGAs against SEU-related disruptions, mainly including the Triple Module Redundancy (TMR) and the configuration scrubbing technology. Collectively, this survey aspires to function as an instructive compendium for engineers and researchers specializing in the development of fault-tolerance mechanisms for SRAM-based FPGAs, particularly in the context of aerospace applications.

The Design of FIR Filter Based on improved DA Algorithm and its FPGA implementation: REVIEW

The Design of FIR Filter Based on improved DA Algorithm and its FPGA implementation: REVIEW

Navigating the electronic landscape: Exploring FPGAs and MCUs architectures in electronic design

Field-Programmable Gate Arrays (FPGAs) and Microcontroller Units (MCUs) are foundational pillars in electronic design, each possessing distinct attributes and applications. This paper embarks on an exploration of these components, delving deep into their unique architectures, performance characteristics, and practical uses. This study, through a comprehensive comparative analysis, examines the strengths and limitations inherent to each of these components. It seeks to serve as a guiding compass for technologists, aiding them in making informed decisions when embarking on electronic design projects. FPGAs emerge as the frontrunners in high-computation endeavors, flexing their computational muscles with finesse. Conversely, MCUs establish their dominance in real-time, low-power applications, where their unwavering reliability is paramount. As electronic systems continue to evolve and infiltrate various aspects of our lives, comprehending the intricacies of FPGA and MCU architectures assumes an increasingly pivotal role for engineers, designers, and researchers. Armed with this knowledge, they can confidently navigate the intricate landscape of electronics, strategically harnessing the power of these two fundamental building blocks to bring innovation and efficiency to the forefront.

An All-digital Compute-in-memory FPGA Architecture for Deep Learning Acceleration

Field Programmable Gate Array (FPGA) is a versatile and programmable hardware platform, which makes it a promising candidate for accelerating Deep Neural Networks (DNNs). However, FPGA’s computing energy efficiency is low due to the domination of energy consumption by interconnect data movement. In this article, we propose an all-digital Compute-in-memory FPGA architecture for deep learning acceleration. Furthermore, we present a bit-serial computing circuit of the Digital CIM core for accelerating vector-matrix multiplication (VMM) operations. A Network-CIM-deployer ( NCIMD ) is also developed to support automatic deployment and mapping of DNN networks. NCIMD provides a user-friendly API of DNN models in Caffe format. Meanwhile, we introduce a Weight-stationary dataflow and describe the method of mapping a single layer of the network to the CIM array in the architecture. We conduct experimental tests on the proposed FPGA architecture in the field of Deep Learning (DL), as well as in non-DL fields, using different architectural layouts and mapping strategies. We also compare the results with the conventional FPGA architecture. The experimental results show that compared to the conventional FPGA architecture, the energy efficiency can achieve a maximum speedup of 16.1×, while the latency can decrease up to 40% in our proposed CIM FPGA architecture.

FPGA Based Air Quality Monitoring System

Abstract: This paper offers a concise review of Air Quality Monitoring Systems employing Field-Programmable Gate Arrays (FPGA). It outlines FPGA architectures, assesses their performance with diverse sensors, discusses integration challenges, and explores recent advancements. Case studies demonstrate practical implementations, validating FPGA's efficacy in delivering real-time, precise air quality data. The review provides valuable insights for future research, contributing to the development of effective and efficient air quality monitoring systems.

Review on FPGA Implementation of CORDIC Algorithm

The Coordinate Rotation Digital Computer (CORDIC) algorithm has emerged as a pivotal method for executing trigonometric and various mathematical operations within digital systems. Field-Programmable Gate Arrays (FPGAs) have witnessed a remarkable surge in adoption for implementing the CORDIC algorithm owing to their inherent flexibility and exceptional performance capabilities. This paper endeavours to provide a comprehensive overview of FPGA implementations of the CORDIC algorithm, elucidating both the advantages and challenges associated with this methodology. It thoroughly examines various FPGA architectures customized for CORDIC implementation, meticulously analyzing their respective trade-offs regarding resource utilization, performance metrics, and accuracy levels. Moreover, the paper explores numerous applications where the FPGA-based CORDIC algorithm shines, illustrating its adaptability across diverse domains like digital signal processing and control systems. These applications underscore the algorithm's efficacy in addressing real-world challenges and its potential to significantly augment system performance and efficiency.By furnishing profound insights into FPGA-based CORDIC implementations, this paper serves as an invaluable resource for engineers and researchers keen on harnessing the capabilities of FPGAs for high-performance mathematical computations in digital systems.

An Approach to the State Explosion Problem: SOPC Case Study

The system on a programmable chip (SOPC) architecture is better than traditional central processing unit (CPU) + field-programmable gate array (FPGA) architecture. It forms an efficient coupling between processor software and programmable logic through an on-chip high-speed bus. The SOPC architecture is resource-rich and highly customizable. At the same time, it combines low power consumption and high performance, making it popular in the field of high reliability and other new industrial fields. The SOPC architecture system is complex and integrates multiple forms of intellectual property (IP). Because of this, the traditional dynamic test and the static test cannot meet the requirements for test depth. To solve the problem of verification depth, we should introduce formal verification. But there are some types of IP forms that formal tools cannot recognize. These include black box IP, encrypted IP, and netlist IP in the SOPC model. Also, the state space explosion caused by the huge scale of the SOPC model cannot be formally verified. In this paper, we propose a modeling method using SOPC architecture. The model solves the problem of formal tools not recognizing multi-form IPs. To compress the state space, we propose reducing SOPC variables and branch relationships based on verification properties. Then, we conduct a property verification experiment on the reduced SOPC model. The experiment result shows that the model can significantly reduce the verification time.

A Flexible System-on-Chip Field-Programmable Gate Array Architecture for Prototyping Experimental Global Navigation Satellite System Receivers

Global navigation satellite system (GNSS) technology is evolving at a rapid pace. The rapid advancement demands rapid prototyping tools to conduct research on new and innovative signals and systems. However, researchers need to deal with the increasing complexity and integration level of GNSS integrated circuits (IC), resulting in limited access to modify or inspect any internal aspect of the receiver. To address these limitations, the authors designed a low-cost System-on-Chip Field-Programmable Gate Array (SoC-FPGA) architecture for prototyping experimental GNSS receivers. The proposed architecture combines the flexibility of software-defined radio (SDR) techniques and the energy efficiency of FPGAs, enabling the development of compact, portable, multi-channel, multi-constellation GNSS receivers for testing novel and non-standard GNSS features with live signals. This paper presents the proposed architecture and design methodology, reviewing the practical application of a spaceborne GNSS receiver and a GNSS rebroadcaster, and introducing the design and initial performance evaluation of a general purpose GNSS receiver serving as a testbed for future research. The receiver is tested, demonstrating the ability of the receiver to acquire and track GNSS signals using static and low Earth orbit (LEO)-scenarios, assessing the observables’ quality and the accuracy of the navigation solutions.

Field programmable gate array‐based energy‐efficient and fast epileptic seizure detection using support vector machine and quadratic discriminant analysis classifier

AbstractEpilepsy is a serious neurological disorder that results in seizures. It can be diagnosed by analyzing the brain's electrical activity using an electroencephalogram (EEG). However, the detection of seizures from massive EEG datasets is a challenging task. To address this challenge, researchers have developed several machine‐learning classifiers and feature extraction techniques for detecting seizures. This paper proposes an energy‐efficient and fast field programmable gate array (FPGA) architecture for detecting epileptic seizures using minimal computational resources. The seizure detection system uses the one Hjorth parameter (mobility) and another statistical parameter (nonlinear energy) as features and employs two efficient classifiers, quadratic discriminant analysis and linear support vector machine (LSVM), for classifying signals into seizure and nonseizure categories. The feature extractor block is connected individually to each of these classifiers. Subsequently, the performance of these two proposed models is evaluated in terms of accuracy, sensitivity, power consumption, resource utilization, and other metrics. The results demonstrate that the SVM classifier‐based model achieved the highest accuracy (99.4%) and sensitivity (98.8%) while consuming minimal dynamic power (0.057 mW) and utilizing the minimum FPGA resources. Thus, the proposed hardware system offers a reliable and energy‐efficient solution for detecting seizures in clinical and real‐time applications.

Lookup Table Merging for FPGA Technology Mapping

Higher logic density is a key goal pursued by Field Programmable Gate Arrays (FPGA). The higher the logic density is, the lower the cost of the circuit spends, and the shorter the line length of the circuit is, the less power is required. Technology mapping is used to map technology-independent logic gates into a lookup table (LUT) netlist. A big problem with the 6-input LUT used in the FPAG at the present stage is that the utilization rate of the lookup table is insufficient. Modern FPGA architectures have good support for dual-output LUTs. We can merge two small LUTs into a new dual-output LUT, if the total number of inputs of the two small LUTs is not greater than the input limit specified by the LUT, thereby reducing the area, that is, reducing the number of LUTs. In this paper, the dual-output LUTs are merged in the technology mapping stage, and a new method of merging single-output LUTs into dual-output LUTs is proposed. The experimental results show that the algorithm used in this paper has an average reduction of 10.21 % in the number of LUTs without worsening delay.

Smart-Redundancy With In Memory ECC Checking: Low-Power SEE-Resistant FPGA Architectures

In harsh environments, such as space, radiation, and charged particles cause single-event effects (SEEs), faults occurring randomly on any electronic component. These must be mitigated to ensure device functionality. Modern mitigation methods, such as triple modular redundancy (TMR), are very effective against single-event transients (SETs) but incur a minimum of 3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> cost in the area. Single-event upsets (SEUs) affect sequential elements and are regularly repaired using memory scrubbing. Scrubbing is a slow serial process going through every memory word, looking for errors to repair. Scrubbing involves a nonnegligible amount of time before an error is detected, during which other events can occur and compromise the system. Field-programmable gate arrays (FPGAs) rely heavily on sequential elements to store their configuration; thus, FPGA’s SEU detection time is critical to ensuring design sustainability in harsh conditions. In this article, we propose an alternative mitigation method based on sensor integration and FPGA architecture modification, called smart-redundancy with in-memory error correction code checking (SRIMECCC). The sensors allow asynchronous SEU detection, reducing the time to detect by 57 250 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> on average and enabling local reconfiguration. Our method includes built-in dual redundancy that reduces the power consumption by 87% on average, benefiting embedded systems. SRIMECCC is also an area-efficient technique that saves 28% of total effective area compared to TMRed designs implemented in FPGAs.

Distributed large-scale graph processing on FPGAs

Processing large-scale graphs is challenging due to the nature of the computation that causes irregular memory access patterns. Managing such irregular accesses may cause significant performance degradation on both CPUs and GPUs. Thus, recent research trends propose graph processing acceleration with Field-Programmable Gate Arrays (FPGA). FPGAs are programmable hardware devices that can be fully customised to perform specific tasks in a highly parallel and efficient manner. However, FPGAs have a limited amount of on-chip memory that cannot fit the entire graph. Due to the limited device memory size, data needs to be repeatedly transferred to and from the FPGA on-chip memory, which makes data transfer time dominate over the computation time. A possible way to overcome the FPGA accelerators’ resource limitation is to engage a multi-FPGA distributed architecture and use an efficient partitioning scheme. Such a scheme aims to increase data locality and minimise communication between different partitions. This work proposes an FPGA processing engine that overlaps, hides and customises all data transfers so that the FPGA accelerator is fully utilised. This engine is integrated into a framework for using FPGA clusters and is able to use an offline partitioning method to facilitate the distribution of large-scale graphs. The proposed framework uses Hadoop at a higher level to map a graph to the underlying hardware platform. The higher layer of computation is responsible for gathering the blocks of data that have been pre-processed and stored on the host’s file system and distribute to a lower layer of computation made of FPGAs. We show how graph partitioning combined with an FPGA architecture will lead to high performance, even when the graph has Millions of vertices and Billions of edges. In the case of the PageRank algorithm, widely used for ranking the importance of nodes in a graph, compared to state-of-the-art CPU and GPU solutions, our implementation is the fastest, achieving a speedup of 13 compared to 8 and 3 respectively. Moreover, in the case of the large-scale graphs, the GPU solution fails due to memory limitations while the CPU solution achieves a speedup of 12 compared to the 26x achieved by our FPGA solution. Other state-of-the-art FPGA solutions are 28 times slower than our proposed solution. When the size of a graph limits the performance of a single FPGA device, our performance model shows that using multi-FPGAs in a distributed system can further improve the performance by about 12x. This highlights our implementation efficiency for large datasets not fitting in the on-chip memory of a hardware device.

X-ray Tomography Reconstruction Accelerated on FPGA through High-Level Synthesis Tools.

Model-Based Iterative Reconstruction (MBIR) algorithms iteratively use expensive computational operators of forward and backward projections. The irregular memory access pattern of these operators makes them a memory-bound application. Their computation time must be reduced to meet clinical routine constraints. This paper proposes a hardware accelerator architecture based on Field Programmable Gate Arrays (FPGAs) through high-level language, as an alternative to GPU architecture. This acceleration is based on an offline memory access analysis to address the main bottleneck of the algorithm and maximize the data reuse rate. The offline analysis allows for the tuning of the architecture parameters so that they converge to an optimal solution. Then, the Berkeley Roofline model guides our optimization steps by iteratively analyzing the design performance. Our design flow significantly improved the algorithm's computational intensity and overcame the memory bottleneck. Thus, our architecture takes advantage of the FPGA local memory to achieve significant memory bandwidth and efficiently harness the pipeline without stalling the computation. Furthermore, we present the scaling-up strategy from mid-range FPGA to high-end FPGA and any concerns of portability. We used two Intel FPGA devices to implement the algorithm, and then we compared the results with our GPU implementation in terms of speedup and energy efficiency. Our experimental results show that our design has achieved better computational throughput than the works on FPGA architectures reported in the literature.

A Methodology for Accelerating FPGA Fault Injection Campaign Using ICAP

The increasing complexity of System-on-Chip (SoC) and the ongoing technology miniaturization on Integrated Circuit (IC) manufacturing processes makes modern SoCs more susceptible to Single-Event Effects (SEE) caused by radiation, even at sea level. To provide realistic estimates at a low cost, efficient analysis techniques capable of replicating SEEs are required. Among these methods, fault injection through emulation using Field-Programmable Gate Array (FPGA) enables campaigns to be run on a Circuit Under Test (CUT). This paper investigates the use of an FPGA architecture to speed up the execution of fault campaigns. As a result, a new methodology for mapping the CUT occupation on the FPGA is proposed, significantly reducing the total number of faults to be injected. In addition, a fault injection technique/flow is proposed to demonstrate the benefits of cutting-edge approaches. The presented technique emulates Single-Event Transient (SET) in all combinatorial elements of the CUT using the Internal Configuration Access Port (ICAP) of Xilinx FPGAs.

Demonstration of FPGA Acceleration of Monte Carlo Simulation

We present results from a stand-alone simulation of electron single Coulomb scattering as implemented completely on an Field Programmable Gate Array (FPGA) architecture and compared with an identical simulation on a standard CPU. FPGA architectures offer unprecedented speed-up capability for Monte Carlo simulations, however with the caveats of lengthy development cycles and resource limitation, particularly in terms of on-chip memory and DSP blocks. As a proof of principle of acceleration on an FPGA, we chose a single scattering process of electrons in water at an energy of 6 MeV. The initial code-base was implemented in C++ and optimised for CPU processing. To measure the potential performance gains of FPGAs compared to modern multi-core CPUs we computed 100M histories of a 6 MeV electron interacting in water. Without performing any hardware-specific optimisation, the results show that the FPGA implementation is over 110 times faster than an optimised parallel implementation running on 12 CPU-cores, and over 270 times faster than a sequential single-core CPU implementation. The results on both architectures were statistically equivalent. The successful implementation and acceleration results are very encouraging for the future exploitation of more sophisticated Monte Carlo simulation on FPGAs for High Energy Physics applications.

Accelerating legacy applications with spatial computing devices

Heterogeneous computing is the major driving factor in designing new energy-efficient high-performance computing systems. Despite the broad adoption of GPUs and other specialized architectures, the interest in spatial architectures like field-programmable gate arrays (FPGAs) has grown. While combining high performance, low power consumption and high adaptability constitute an advantage, these devices still suffer from a weak software ecosystem, which forces application developers to use tools requiring deep knowledge of the underlying system, often leaving legacy code (e.g., Fortran applications) unsupported. By realizing this, we describe a methodology for porting Fortran (legacy) code on modern FPGA architectures, with the target of preserving performance/power ratios. Aimed as an experience report, we considered an industrial computational fluid dynamics application to demonstrate that our methodology produces synthesizable OpenCL codes targeting Intel Arria10 and Stratix10 devices. Although performance gain is not far beyond that of the original CPU code (we obtained a relative speedup of times 0.59 and times 0.63, respectively, for a single optimized main kernel, while only on the Stratix10 we achieved times 2.56 by replicating the main optimized kernel 4 times), our results are quite encouraging to drawn the path for further investigations. This paper also reports some major criticalities in porting Fortran code on FPGA architectures.

Measurement of Ultrasound Propagation Velocity in Liquids Using an FPGA Module

The design and development of an ultrasonic device for the measurement of ultrasonic propagation velocity in liquids based on Field Programmable Gate Array (FPGA) architecture is described. The device was implemented using a DE0-Nano-SoC Development Kit FPGA development module, a 2x16 LCD Display, a 2-channel quadrature output optical encoder with push button, two ultrasonic transducers and an external module for interfacing with the transducers containing the circuits corresponding to the transmitter, receiver and amplifier. For the development, the Altera Integrated Development Environment (IDE) software called Quartus II was used, which allows the logical design and supports different HDL hardware description languages, such as Verilog and VHLD. Although the device was calibrated to measure the acoustic velocity of water in the range of 35°C to 40°C, due to its design characteristics it is feasible to extend its application to measure acoustic velocity in different liquids, delimiting the operation intervals. The device acquires 100 readings per second, calculates the average with polynomial adjustment and displays the value of the ultrasonic propagation velocity in the fluid with a resolution of 0.01 [m/s] with a refresh rate of one second.

Mesh of Trees FPGA Architecture: Exploration and Optimization

The design of large devices suggests fundamental and efficient innovation in the field programmable gate array (FPGA) interconnect structure to improve power consumption, density, and performance. Mesh-based FPGA architectures are generally designed to maximize logic utilization and to ensure layout scalability whereas tree-based FPGA architectures are designed to increase interconnect utilization. In this article, we propose a new mesh of trees (MoTs) FPGA architecture where we try to benefit from mesh of clusters (MoCs) FPGA layout scalability and tree-based FPGA efficient intracluster interconnect utilization, thanks to the butterfly fat-tree (BFT) topology. In order to attain the efficient use of the proposed routing interconnect resources, we develop computer-aided design (CAD) tools that respond to the target MoTs FPGA features. In addition, we define the power, area, and delay metric models according to the proposed architecture criteria. The experimentation results show that MoTs architecture with a cluster arity 32 offers the best tradeoff between power, area, and delay. Furthermore, we conduct a comparison between MoTs and MoCs FPGAs in general and the best MoTs and MoCs solutions, which ensure the best tradeoff between power, area, and delay in particular. The results show that the best MoTs architecture reduces power, area, delay, and energy by an average of 29%, 6%, 40%, and 47%, respectively, in comparison with the best MoCs architecture.