Field Programmable Gate Array Unit Research Articles

Research on Development 3D Ground Penetrating Radar Acquisition and Control Technology for Road Underground Diseases with Dual-Band Antenna Arrays.

This paper describes the development of a new 3D ground-penetrating radar (GPR) acquisition and control technology for road underground diseases with dual-band antenna arrays. The 3D GPR system can be mounted on a vehicle-loading device and used by vehicles to detect road underground diseases at regular speeds. Compared with existing 3D GPR systems, this new type of 3D GPR has the following design features: it has dual-band antenna arrays, including a 16-channel 400 MHz antenna array and an 8-channel 200 MHz antenna array, which not only improves the detection efficiency, but also effectively balances the detection depth and detection resolution. A novel antenna switching method for time division step multiplexing (TDSM) is realized via field programmable gate array (FPGA), which not only avoids the crosstalk of antenna echo signals of different frequencies, but also ensures the interval of the same antenna working time. By combining the advantages of the FPGA and micro-control unit (MCU), and utilizing the high-speed transmission of the network port, the high-speed real-time transmission of the 3D GPR echo data is achieved. Finally, the integration of all software and hardware verified the correctness of the system, with good results.

Secure Video Streaming Using Dedicated Hardware

The purpose of this article is to present a system that enhances the security, efficiency, and reconfigurability of an Internet-of-Things (IoT) system used for surveillance and monitoring. A Multi-Processor System-On-Chip (MPSoC) composed of Central Processor Unit (CPU) and Field-Programmable Gate Array (FPGA) is proposed for increasing the security and the frame rate of a smart IoT edge device. The private encryption key is safely embedded in the FPGA unit to avoid being exposed in the Random Access Memory (RAM). This allows the edge device to securely store and authenticate the key, protecting the data transmitted from the same Integrated Circuit (IC). Additionally, the edge device can simultaneously publish and route a camera stream using a lightweight communication protocol, achieving a frame rate of 14 frames per Second (fps). The performance of the MPSoC is compared to a NVIDIA Jetson Nano (NJN) and a Raspberry Pi 4 (RPI4) and it is found that the RPI4 is the most cost-effective solution but with lower frame rate, the NJN is the fastest because it can achieve higher frame-rate but it is not secure, and the MPSoC is the optimal solution because it offers a balanced frame rate and it is secure because it never exposes the secure key into the memory. The proposed system successfully addresses the challenges of security, scalability, and efficiency in an IoT system used for surveillance and monitoring. The Rivest-Shamir-Adleman (RSA) encryption key is securely stored and authenticated, and the edge device is able to simultaneously publish and route a camera stream feed high-definition images at 14 fps. The proposed system enhances the security, efficiency, and reconfigurability of an IoT system used for surveillance and monitoring. The RSA encryption key is effectively protected by the implementation of an MPSoC with Programmable Logic (PL), which also allows for faster processing and data transmission.

Real-time signal processing system based on FPGA for motional Stark effect diagnostic on EAST.

The plasma current density profile plays a key role in the development of a high poloidal beta scenario, which is essential for long-pulse and high-performance plasma operation on a tokamak. Based on the polarimetry technique, a Motional Stark Effect (MSE) diagnostic has been built on the Experimental Advanced Superconducting Tokamak. To be prepared for real-time (RT) feedback control of the plasma current density profile in the future, a RT signal processing system has been developed. The RT signal processing system is composed of three functional modules: analog-to-digital conversion (ADC) module, polarization information extraction module, and digital-to-analog conversion (DAC) module. The final objective of this system is to acquire the polarization information of the MSE. Based on the field-programmable gate array unit, fast Fourier transformation is adopted to process the Photoelastic Modulator (PEM) digital signal, which was converted from a PEM signal via the ADC module. By means of frequency spectrum separation, the components around double modulating frequencies are restored through inverse fast Fourier transformation. Furthermore, the two amplitudes of their corresponding components can be obtained through a digital harmonic analyzer technique. Afterward, the ratio of the two amplitudes is calculated by arc tangent so that the polarization angle is obtained. Finally, the information of this polarization angle is converted into a voltage signal by the DAC module and then output in RT. The test results based on the RT signal processing system are in good agreement with those based on the phase lock-in amplifiers. The working cycle of this system is shorter than 10ms, which meets the requirements of the MSE diagnostic as a RT controller. The algorithm of RT signal processing and the relevant technology applied for building this system are presented in the main body of this paper in detail.

Achievement of stable negative ion production with Cs-seeded for long pulse beam operation in the prototype of Cs-seeded negative ion source for JT-60SA.

Long pulse negative ion beams of 500 keV and 154 A/m2 for 118 s have been achieved for the first time, which exceeds the requirement of the JT-60SA negative ion source. In order to solve the issues of such long pulse beams, the fast cutoff system of the power supply aims to reduce the surge current and to extend the lifetime of filaments and the suppression method of excess cesium (Cs) accumulation on the plasma grid (PG) to achieve stable negative ion production. By developing the fast cutoff system using a field programmable gate array unit for the arc power supply, the cutoff time has been reduced to 1/10 that of the original system and the lifetime of the filament was extended by three times. In order to achieve stable negative ion production, incoming Cs on the PG surface has been reduced by keeping the chamber wall temperature below 40 °C. As a result, a stable beam current drift of <6% has been achieved for the 118 s duration.

A Cost-Efficient Real-Time 25 Mb/s System for LED-UOWC: Design, Channel Coding, FPGA Implementation, and Characterization

In this paper, we experimentally demonstrate a cost-efficient real-time field programmable gate array (FPGA)-based system for underwater optical wireless communication (UOWC) at a data rate up to 25 Mb/s over a 10 m underwater channel. The transmitter of the system employs a commercial blue LED as a modulation light source and an FPGA unit for transmitter baseband signal processing, and an avalanche photo diode cascaded with an FPGA unit for receiver baseband signal processing at the receiver side. We also suggest a simplified system model to characterize underwater optical link. Three types of hard-decision forward error correction codes are introduced to investigate the impact on the receiver sensitivity in long distance transmission cases. By adding additional link attenuation, we experimentally measure the attenuation coefficients for different water conditions. Based on the measured results, the achievable link distance for clear ocean water is estimated up to 118 m at the transmitted electrical power of 30 dBm. The proposed UOWC system takes both implementation complexity and cost into consideration and also provides a significant guidance to the future real-time high-speed underwater optical communications.

A Repetitive Solid State Marx-Type Pulsed Power Generator Using Multistage Switch-Capacitor Cells

This paper reports on the novel development of a fully solid state Marx-type circuit to achieve output voltage pulses with adjustable voltage levels, pulse width, and frequency using a series connection of half-bridge or full-bridge switch-capacitor cells (SCC). Modularity of the circuit allows independent control of each SCC, resulting in more freedom to control the pulsed power parameters. A 3-kW laboratory prototype of the proposed generator topology was implemented using 1700-V insulated gate bipolar transistors (IGBTs) and a 1-kV power supply. The SCC unit circuit board is stacked to increase the maximum output voltage. The control unit for the output pulse parameters was performed using an field-programmable gate array unit.

A field programmable gate array unit for the diagnosis and control of neoclassical tearing modes on MAST

A real-time system has been developed to trigger both the MAST Thomson scattering (TS) system and the plasma control system on the phase and amplitude of neoclassical tearing modes (NTMs), extending the capabilities of the original system. This triggering system determines the phase and amplitude of a given NTM using magnetic coils at different toroidal locations. Real-time processing of the raw magnetic data occurs on a low cost field programmable gate array (FPGA) based unit which permits triggering of the TS lasers on specific amplitudes and phases of NTM evolution. The MAST plasma control system can receive a separate trigger from the FPGA unit that initiates a vertical shift of the MAST magnetic axis. Such shifts have fully removed m∕n = 2∕1 NTMs instabilities on a number of MAST discharges.

Novel cascade FPGA accelerator for support vector machines classification.

Support vector machines (SVMs) are a powerful machine learning tool, providing state-of-the-art accuracy to many classification problems. However, SVM classification is a computationally complex task, suffering from linear dependencies on the number of the support vectors and the problem's dimensionality. This paper presents a fully scalable field programmable gate array (FPGA) architecture for the acceleration of SVM classification, which exploits the device heterogeneity and the dynamic range diversities among the dataset attributes. An adaptive and fully-customized processing unit is proposed, which utilizes the available heterogeneous resources of a modern FPGA device in efficient way with respect to the problem's characteristics. The implementation results demonstrate the efficiency of the heterogeneous architecture, presenting a speed-up factor of 2-3 orders of magnitude, compared to the CPU implementation. The proposed architecture outperforms other proposed FPGA and graphic processor unit approaches by more than seven times. Furthermore, based on the special properties of the heterogeneous architecture, this paper introduces the first FPGA-oriented cascade SVM classifier scheme, which exploits the FPGA reconfigurability and intensifies the custom-arithmetic properties of the heterogeneous architecture. The results show that the proposed cascade scheme is able to increase the heterogeneous classifier throughput even further, without introducing any penalty on the resource utilization.