Field Programmable Gate Array Platform Research Articles

A New Optimized Hybridization Approach for in silico High Throughput Molecular Docking on FPGA Platform.

The development process of a new drug should be a subject of continuous evolution and rapid improvement as drugs are essential to treat a wide range of diseases of which many are life-threatening. The advances in technology resulted in a novel track in drug discovery and development known as in silico drug design. The molecular docking phase plays a vital role in in silico drug development process. In this phase, thousands of 3D conformations of both the ligand and receptor are generated and the best conformations that create the most stable drug-receptor complex are determined. The speed in finding accurate and high-quality complexes depends on the efficiency of the search function in the molecular docking procedure. The objective of this research is to propose and implement a novel hybrid approach called hABCDE to replace the EMC searching part inside the BUDE docking algorithm. This helps in reaching the best solution in a much accelerated time and higher solution quality compared to using the ABC and DE algorithms separately. In this work, we have employed a new approach of hybridization between the Artificial Bee Colony (ABC) algorithm and the Differential Evolution (DE) algorithm as an alternative searching part of the Bristol University Docking Engine (BUDE) in order to accelerate the search for higher quality solutions. Moreover, the proposed docking approach was implemented on Field Programmable Gate Array (FPGA) parallel platform using Vivado High-Level Synthesis Tool (HLST) in order to optimize and enhance the execution time and overall efficiency. The NDM-1 protein was used as a model receptor in our experiments to demonstrate the efficiency of our approach. The NDM-1 protein was used as a model receptor in our experiments to demonstrate the efficiency of our approach. The results showed that the execution time for the BUDE with the new proposed hybridization approach was improved by 9,236 times. Our novel approach was significantly effective to improve the functionality of docking algorithms (Bristol University Docking Engine (BUDE)).

Enhancing energy efficiency in tyre pressure and temperature monitoring systems

This study addresses the pivotal challenge of enhancing power efficiency in tyre pressure and temperature monitoring systems (TPMS) for heavy vehicles and trailers. Employing field-programmable gate arrays (FPGA) and adaptive channel frequency hopping in bluetooth low energy (BLE) communication, the research focuses on mitigating power consumption issues specific to heavy vehicles with multiple tyres. The proposed solution incorporates strategic BLE channel blocking and adaptive frequency hopping on the FPGA platform to alleviate channel congestion and interference, ultimately reducing TPMS power consumption. The FPGA's adaptability tailors frequency hopping strategies to automotive TPMS nuances, optimizing channel selection and minimizing energy-intensive processes. Empirical results showcase a significant reduction in power consumption, with the TPMS operating at 100 MHz during active mode consuming 66 mW, dropping to 11 mW in sleep mode, and reaching 0 mW in hibernate mode for the majority of operational time. This research establishes a practical FPGA-based approach for power optimization in commercial TPMS, promising heightened reliability, safety improvements, and environmental impact reduction in the automotive sector.

Exploring memory synchronization and performance considerations for FPGA platform using the high-abstracted OpenCL framework: Benchmarks development and analysis.

A key benefit of the Open Computing Language (OpenCL) software framework is its capability to operate across diverse architectures. Field programmable gate arrays (FPGAs) are a high-speed computing architecture used for computation acceleration. This study investigates the impact of memory access time on overall performance in general FPGA computing environments through the creation of eight benchmarks within the OpenCL framework. The developed benchmarks capture a range of memory access behaviors, and they play a crucial role in assessing the performance of spinning and sleeping on FPGA-based architectures. The results obtained guide the formulation of new implementations and contribute to defining an abstraction of FPGAs. This abstraction is then utilized to create tailored implementations of primitives that are well-suited for this platform. While other research endeavors concentrate on creating benchmarks with the Compute Unified Device Architecture (CUDA) to scrutinize the memory systems across diverse GPU architectures and propose recommendations for future generations of GPU computation platforms, this study delves into the memory system analysis for the broader FPGA computing platform. It achieves this by employing the highly abstracted OpenCL framework, exploring various data workload characteristics, and experimentally delineating the appropriate implementation of primitives that can seamlessly integrate into a design tailored for the FPGA computing platform. Additionally, the results underscore the efficacy of employing a task-parallel model to mitigate the need for high-cost synchronization mechanisms in designs constructed on general FPGA computing platforms.

Reg-Tune: A Regression-Focused Fine-Tuning Approach for Profiling Low Energy Consumption and Latency

Fine-tuning deep neural networks is pivotal for creating inference modules that can be suitably imported to edge or field-programmable gate array (FPGA) platforms. Traditionally, exploration of different parameters throughout the layers of deep neural networks has been done using grid search and other brute force techniques. Although these methods lead to the optimal choice of network parameters, the search process can be very time consuming and may not consider deployment constraints across different target platforms. This work addresses this problem by proposing Reg-Tune, a regression-based profiling approach to quickly determine the trend of different metrics in relation to hardware deployment of neural networks on tinyML platforms like FPGAs and edge devices. We start by training a handful of configurations belonging to different combinations of \(\mathcal {NN}\scriptstyle \langle q (quantization),\,s (scaling)\rangle \displaystyle\) or \(\mathcal {NN}\scriptstyle \langle r (resolution),\,s\rangle \displaystyle\) workloads to generate the accuracy values respectively for their corresponding application. Next, we deploy these configurations on the target device to generate energy/latency values. According to our hypothesis, the most energy-efficient configuration suitable for deployment on the target device is a function of the variables q , r , and s . Finally, these trained and deployed configurations and their related results are used as data points for polynomial regression with the variables q , r , and s to realize the trend for accuracy/energy/latency on the target device. Our setup allows us to choose the near-optimal energy-consuming or latency-driven configuration for the desired accuracy from the contour profiles of energy/latency across different tinyML device platforms. To this extent, we demonstrate the profiling process for three different case studies and across two platforms for energy and latency fine-tuning. Our approach results in at least 5.7 \(\times\) better energy efficiency when compared to recent implementations for human activity recognition on FPGA and 74.6% reduction in latency for semantic segmentation of aerial imagery on edge devices compared to baseline deployments.

AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-Based Lightweight PQC

Lightweight PQC-related research and development have gradually gained attention from the research community recently. Ring-Binary-Learning-with-Errors (RBLWE)-based encryption scheme (RBLWE-ENC), a promising lightweight PQC based on small parameter sets to fit related applications (but not in favor of deploying popular fast algorithms like number theoretic transform). To solve this problem, in this article, we present a novel implementation of hardware acceleration for RBLWE-ENC based on Karatsuba algorithm, particularly on the field-programmable gate array (FPGA) platform. In detail, we have proposed an area-efficient Karatsuba Accelerator (AEKA) for RBLWE-ENC, based on three layers of innovative efforts. First of all, we reformulate the signal processing sequence within the major arithmetic component of the KA-based polynomial multiplication for RBLWE-ENC to obtain a new algorithm. Then, we have designed the proposed algorithm into a new hardware accelerator with several novel algorithm-to-architecture mapping techniques. Finally, we have conducted thorough complexity analysis and comparison to demonstrate the efficiency of the proposed accelerator, e.g., it involves 62.5% higher throughput and 60.2% less area-delay product (ADP) than the state-of-the-art design for n =512 (Virtex-7 device, similar setup). The proposed AEKA design strategy is highly efficient on the FPGA devices, i.e., small resource usage with superior timing, which can be integrated with other necessary systems for lightweight-oriented high-performance applications (e.g., servers). The outcome of this work is also expected to generate impacts for lightweight PQC advancement.

ADS-CNN: Adaptive Dataflow Scheduling for lightweight CNN accelerator on FPGAs

Lightweight convolutional neural networks (CNNs) enable lower inference latency and data traffic, facilitating deployment on resource-constrained edge devices such as field-programmable gate arrays (FPGAs). However, CNNs inference requires access to off-chip synchronous dynamic random-access memory (SDRAM), which significantly degrades inference speed and system power efficiency. In this paper, we propose an adaptive dataflow scheduling method for lightweight CNN accelerator on FPGAs named ADS-CNN. The key idea of ADS-CNN is to efficiently utilize on-chip resources and reduce the amount of SDRAM access. To achieve the reuse of logical resources, we design a time division multiplexing calculation engine to be integrated in ADS-CNN. We implement a configurable module for the convolution controller to adapt to the data reuse of different convolution layers, thus reducing the off-chip access. Furthermore, we exploit on-chip memory blocks as buffers based on the configuration of different layers in lightweight CNNs. On the resource-constrained Intel CycloneV SoC 5CSEBA6 FPGA platform, we evaluated six common lightweight CNN models to demonstrate the performance advantages of ADS-CNN. The evaluation results indicate that, compared with accelerators that use traditional tiling strategy dataflow, our ADS-CNN can achieve up to 1.29× speedup with the overall dataflow scale compression of 23.7%.

FPGA-Based Speed Control Strategy of PMSM Using Improved Beetle Antennae Search Algorithm

To improve performance in terms of overshoot and motor response speed when a permanent-magnet synchronous motor (PMSM) with a proportional–integral (PI) controller is subjected to external disturbances, this paper proposes a speed control strategy based on an enhanced Beetle Antennae Search algorithm, which allows for adjustable parameters of the PI controller within a certain range. Firstly, to enhance the global and local search capabilities of each individual beetle, the step size was improved by linearly decreasing it. Secondly, a simulation model of a PMSM closed-loop control system was built to verify the effectiveness of the improved Beetle Antennae Search (BAS) algorithm. Finally, a linear feedback shift register model that generates four random numbers was developed on a field-programmable gate array (FPGA). The improved BAS algorithm for the PMSM control system was implemented on an FPGA using the Verilog hardware description language, and the feasibility of the system was verified through hardware simulation. Additionally, the hardware resource consumption on different FPGA platforms was analyzed. The simulation results demonstrate that the proposed new speed control strategy can reduce the overshoot and improve the motor response speed.

Optimizing Neural Network Inference in Edge Robotics by Harnessing FPGA Hardware Acceleration

This research explores advancements in neural network inference for edge robotics through the implementation of hardware acceleration using Field-Programmable Gate Arrays (FPGA). Leveraging FPGA's versatility in custom hardware design, the research optimizes performance and energy efficiency by utilizing features such as Digital Signal Processors (DSP), Multiply-Accumulate (MAC) arrays, parallel processing units, Convolutional Neural Networks (CNN), and custom accelerators. The computational power of FPGA-based architectures is harnessed to significantly enhance the speed and efficiency of neural network inference tasks in edge robotics applications. Key aspects include the utilization of DSP blocks for efficient signal processing, MAC arrays for high-speed matrix operations crucial in neural network computations, and parallel processing units for concurrent execution of multiple tasks, improving overall system throughput. The integration of CNN directly onto FPGA hardware allows for minimal-latency inference, making it ideal for real-time applications in edge robotics scenarios. Custom accelerators tailored to specific neural network operations further optimize performance and resource utilization. The research involves the meticulous design and synthesis of hardware modules tailored to the target FPGA platform. Through rigorous optimization and parallelization techniques, the goal is to maximize resource utilization while minimizing latency and power consumption. The experimental findings showcase remarkable results, including a substantial increase in throughput, with values reaching up to 150 images/sec, and impressive accuracy rates exceeding 95% in classification tasks.

Voltage Scaled Low Power DNN Accelerator Design on Reconfigurable Platform

The exponential emergence of Field-Programmable Gate Arrays (FPGAs) has accelerated research on hardware implementation of Deep Neural Networks (DNNs). Among all DNN processors, domain-specific architectures such as Google’s Tensor Processor Unit (TPU) have outperformed conventional GPUs (Graphics Processing Units) and CPUs (Central Processing Units). However, implementing low-power TPUs in reconfigurable hardware remains a challenge in this field. Voltage scaling, a popular approach for energy savings, can be challenging in FPGAs, as it may lead to timing failures if not implemented appropriately. This work presents an ultra-low-power FPGA implementation of a TPU for edge applications. We divide the systolic array of a TPU into different FPGA partitions based on the minimum slack value of different design paths of Multiplier Accumulators (MACs). Each partition uses different near-threshold (NTC) biasing voltages to run its FPGA cores. The biasing voltage for each partition is roughly calculated by the proposed static schemes. However, further calibration of biasing voltage is performed by the proposed runtime scheme. To overcome the timing failure caused by NTC, the MACs with higher minimum slack are placed in lower-voltage partitions, while the MACs with lower minimum slack paths are placed in higher-voltage partitions. The proposed architecture is implemented in a commercial platform, namely Vivado with Xilinx Artix-7 FPGA and academic platform VTR with 22 nm, 45 nm and 130 nm FPGAs. Any timing error caused by NTC can be caught by the Razor flipflop used in each MAC. The proposed voltage-scaled, partitioned systolic array can save 3.1% to 11.6% of dynamic power in Vivado and VTR tools, respectively, depending on the FPGA technology, partition size, number of partitions and biasing voltages. The normalized performance and accuracy of benchmark models running on our low-power TPU are very competitive compared to existing literature.

Survey of convolutional neural network accelerators on field-programmable gate array platforms: architectures and optimization techniques

Survey of convolutional neural network accelerators on field-programmable gate array platforms: architectures and optimization techniques

Power Optimization in Wireless Sensor Network Using VLSI Technique on FPGA Platform

Nowadays, the demand for high-performance wireless sensor networks (WSN) is increasing, and its power requirement has threatened the survival of WSN. The routing methods cannot optimize power consumption. To improve the power consumption, VLSI based power optimization technology is proposed in this article. Different elements in WSN, such as sensor nodes, modulation schemes, and package data transmission, influence energy usage. Following a WSN power study, it was discovered that lowering the energy usage of sensor networks is critical in WSN. In this manuscript, a power optimization model for wireless sensor networks (POM-WSN) is proposed. The proposed system shows how to build and execute a power-saving strategy for WSNs using a customized collaborative unit with parallel processing capabilities on FPGA (Field Programmable Gate Array) and a smart power component. The customizable cooperation unit focuses on applying specialized hardware to customize Operating System speed and transfer it to a soft intel core. This device decreases the OS (Operating System) central processing unit (CPU) overhead associated with installing processor-based IoT (Internet of Things) devices. The smart power unit controls the soft CPU’s clock and physical peripherals, putting them in the right state depending on the hardware requirements of the program (tasks) being executed. Furthermore, by taking the command signal from a collaborative custom unit, it is necessary to adjust the amplitude and current. The efficiency and energy usage of the FPGA-based energy saver approach for sensor nodes are compared to the energy usage of processor-based WSN nodes implementations. Using FPGA programmable architecture, the research seeks to build effective power-saving approaches for WSNs.

Systematic analysis of FPGA-based hardware accelerators for convolutional neural networks

In the modern era, machine learning stands as a pivotal component of artificial intelligence, exerting a profound impact on various domains. This article delineates a methodology for designing and applying Field Programmable Gate Array (FPGA) based hardware accelerators for convolutional neural networks (CNNs). Initially, this paper introduces CNNs, a subset of deep learning techniques, and underscore their pivotal role in artificial intelligence, spanning domains such as image recognition, speech processing, and natural language understanding. Subsequently, we delve into the intricacies of FPGA, an adaptable logic device characterized by high integration and versatility, elucidating our approach to creating a hardware accelerator tailored for CNNs on the FPGA platform. To enhance computational efficiency, we employ technical strategies like dual cache structures, loop unrolling, and loop tiling for accelerating the convolutional layers. Finally, through empirical experiments employing YOLOv2, and validate the efficacy and superiority of our designed hardware accelerator model. This paper anticipates that in the forthcoming years, the methodology and research into FPGA-based CNN hardware accelerators will yield even more substantial contributions, propelling the advancement and widespread adoption of deep learning technology.

Pflow: An end-to-end heterogeneous acceleration framework for CNN inference on FPGAs

Field-Programmable Gate Arrays (FPGAs), renowned for their high performance per watt, are extensively utilized to accelerate Convolutional Neural Networks (CNNs) in edge computing environments, primarily employing dataflow-based and instruction set-based approaches. Compared to the instruction set-based approach that features fast and versatile circuit design, the dataflow-based approach can significantly enhance performance at the expense of design versatility. Nevertheless, edge computing environments require both high energy efficiency and adaptability to various scenarios. This paper proposes a novel end-to-end heterogeneous acceleration framework for CNN inference on FPGAs, named Pflow. The basic idea is to decouple network deployment and hardware details with a hardware–software co-design approach. First, a dataflow accelerator with an adaptive scheduling strategy is proposed. The adaptive scheduling strategy, along with a scalable design, maximizes hardware utilization in terms of computing resources and bandwidth. Secondly, we design a novel operator-perception method to automate the processes of network reconstruction and operator fusion. Thirdly, we integrate Pflow into the industrial-grade deep learning framework Paddle-Lite. We evaluate Pflow by implementing several networks on two representative FPGA platforms. Experimental results demonstrate that Pflow achieves energy efficiencies of 46.5 GOPS/W on Xilinx Zynq Ultrascale+ MPSoC 3EG and 59.4 GOPS/W on Virtex UltraScale+ XCVU13P. It also reaches a throughput of up to 255.7 GOPS on the former and 3.686 TOPS on the latter.

CASA: A Compact and Scalable Accelerator for Approximate Homomorphic Encryption

Approximate arithmetic-based homomorphic encryption (HE) scheme CKKS [CKKS17] is arguably the most suitable one for real-world data-privacy applications due to its wider computation range than other HE schemes such as BGV [BGV14], FV and BFV [Bra12, FV12]. However, the most crucial homomorphic operation of CKKS called key-switching induces a great amount of computational burden in actual deployment situations, and creates scalability challenges for hardware acceleration. In this paper, we present a novel Compact And Scalable Accelerator (CASA) for CKKS on the field-programmable gate array (FPGA) platform. The proposed CASA addresses the aforementioned computational and scalability challenges in homomorphic operations, including key-exchange, homomorphic multiplication, homomorphic addition, and rescaling.On the architecture layer, we propose a new design methodology for efficient acceleration of CKKS. We design this novel hardware architecture by carefully studying the homomorphic operation patterns and data dependency amongst the primitive oracles. The homomorphic operations are efficiently mapped into an accelerator with simple control and smooth operation, which brings benefits for scalable implementation and enhanced pipeline and parallel processing (even with the potential for further improvement).On the component layer, we carry out a detailed and extensive study and present novel micro-architectures for primitive function modules, including memory bank, number theoretic transform (NTT) module, modulus switching bank, and dyadic multiplication and accumulation.On the arithmetic layer, we develop a new partially reduction-free modular arithmetic technique to eliminate part of the reduction cost over different prime moduli within the moduli chain of the Residue Number System (RNS). The proposed structure can support arbitrary numbers of security primes of CKKS during key exchange, which offers better security options for adopting the scalable design methodology.As a proof-of-concept, we implement CASA on the FPGA platform and compare it with state-of-the-art designs. The implementation results showcase the superior performance of the proposed CASA in many aspects such as compact area, scalable architecture, and overall better area-time complexities.In particular, we successfully implement CASA on a mainstream resource-constrained Artix-7 FPGA. To the authors’ best knowledge, this is the first compact CKKS accelerator implemented on an Artix-7 device, e.g., CASA achieves a 10.8x speedup compared with the state-of-the-art CPU implementations (with power consumption of only 5.8%). Considering the power-delay product metric, CASA also achieves 138x and 105x improvement compared with the recent GPU implementation.

Asymmetrical multi‐level inverter by using space vector pulse width modulation technique for low and medium power applications

SummaryA DC to AC converter is developed in this paper. This proposes a single‐phase five‐level inverter is developed in such a way that one DC source is used. The structure of the inverter is modular and the capacitor has self‐voltage balancing capability, which eliminates the need for sensors or an additional control loop. This paper presents the schematic diagram of the proposed topology, principle of operation, and the concepts of sinusoidal pulse width modulation (SPWM) for single‐phase and space vector pulse width modulation (SVPWM) for three‐phase. To further prove the advantage, power loss, and parameter computations are calculated mathematically. Low‐voltage stress is achieved in the proposed topology because the blocking voltages of all the switches are constrained to the input voltage. A comparison table is presented between SPWM and SVPWM schemes in three‐phase inverter. The proposed asymmetrical five‐level configuration setup is constructed, and experiments are performed inside the laboratory. The controller of the converter has been implemented in the field‐programmable gate array (FPGA) platform. In order to confirm the viability of the suggested topology, experimental results are provided for single‐phase arrangement. By using the FPGA platform, real‐time implementation is done for a three‐phase inverter topology.

The Data Compression Method and FPGA Implementation in the Mars Rover Subsurface-Penetrating Radar on the Tianwen-1 Mission

Since Mars is far away from Earth, the propagation delay between Mars and Earth is very large. To ensure the effective use of the link transmission bandwidth, China’s first Mars exploration mission has put forward a demand for data compression for all scientific payloads. The on-board mature algorithms for data compression are mainly focused on optical images and microwave imaging radar applications. No articles have been published on data compression methods that are applied to subsurface-penetrating radar. Based on the background of this application, this paper proposes a logarithmic lossy compression algorithm which can meet the mission requirements for high compression ratios of 4:1 and 2.5:1. Its compression error is less than that of the block adaptive quantization (BAQ) algorithm. The algorithm is not only easy to implement on field-programmable gate array (FPGA) platforms, but also offers simple ground decompression and fast imaging. The experimental results show that high compression ratios of 4:1 and 2.5:1 can be realized, even if the data in and between traces do not have a strong correlation. And its relative error is less than 2%, which is a new type of high-efficiency data compression method that can be implemented on-board to meet with the demand of subsurface penetrating radar.

Marine magnetotelluric and controlled source electromagnetics signal simulative generator

Ocean bottom electromagnetic receivers (OBEMs) are invaluable tools for observing seafloor electromagnetic signals, primarily used in magnetotelluric (MT) sounding and marine controlled source electromagnetics (MCSEM). However, the high operational costs of deploying OBEMs require thorough pre-deployment testing to enhance the data reliability and quality. Commercial signal generators used for MT and controlled source electromagnetic (CSEM) testing often fall short of the restricted terms of the frequency range, signal-to-noise ratio, storage depth, time synchronization, and amplitude dynamics. To address these limitations, we developed a specialized marine MT and CSEM signal simulative generator. The generator employs pseudorandom number code-based white noise to simulate MT signals and uses multi-frequency synthesis and amplitude modulation (AM) to generate CSEM signals. The system is developed using a low-power microcontroller unit and a field programmable gate array platform, integrating various circuits such as power, clock, encoding, control, data storage, chopper, and amplification circuits. The generator simultaneously outputs four-channel white noise and AM signals. The white noise feature provides a wide and adjustable frequency band and amplitude, while the AM feature provides a large dynamic amplitude range and multi-frequency synthesis at various carrier frequency points. Comprehensive testing verified the performance of the proposed simulative generator. The test results demonstrate that the MT simulated signals cover a frequency range from 1 E4s to 100 Hz, providing adjustable amplitudes between 10 μVpp and 10 mVpp. The CSEM simulated signals include standard square waves, third harmonic waves, and seventh harmonic waves, with amplitudes adjustable from 10 mVpp to 10 Vpp. The proposed simulative generator enhances the efficiency of OBEM functional testing and provides essential equipment support for maintaining the quality of marine data.

Investigating the efficiency and performance gains of FPGA-accelerated Convolutional Neural Networks

With the rise of big data and artificial intelligence (AI), Convolutional Neural Networks (CNNs) have become instrumental in numerous applications, from image and speech recognition to natural language processing. However, these networks computational demands often exceed the capabilities of traditional processing units, leading to a search for more effective computing platforms. This research aims to evaluate the potential of Field-Programmable Gate Array (FPGA) technology in accelerating CNN computations, considering FPGAs unique attributes such as reprogrammability, energy efficiency, and custom logic potential. The primary aim of this research is to compare the efficiency and performance of FPGA acceleration of CNNs with conventional processing units like CPUs and GPUs and to explore its potential for future AI applications. This research employs a mixed-methods approach, including an integrated literature review and comparative analysis. This paper reviews state-of-the-art research on FPGA-accelerated CNNs, benchmark performance metrics of FPGA, CPU, and GPU platforms across various CNN models, and compare FPGA-based AI applications with other real-world AI applications. The findings suggest a significant potential for FPGA-accelerated CNNs, particularly in scenarios requiring real-time computation or power-limited environments. However, challenges persist in the areas of development complexity and limited on-chip memory. Future work must focus on surmounting these barriers to unlock the full potential of FPGA-accelerated CNNs.

Hardware Implementations of a Deep Learning Approach to Optimal Configuration of Reconfigurable Intelligence Surfaces

Reconfigurable intelligent surfaces (RIS) offer the potential to customize the radio propagation environment for wireless networks, and will be a key element for 6G communications. However, due to the unique constraints in these systems, the optimization problems associated to RIS configuration are challenging to solve. This paper illustrates a new approach to the RIS configuration problem, based on the use of artificial intelligence (AI) and deep learning (DL) algorithms. Concretely, a custom convolutional neural network (CNN) intended for edge computing is presented, and implementations on different representative edge devices are compared, including the use of commercial AI-oriented devices and a field-programmable gate array (FPGA) platform. This FPGA option provides the best performance, with ×20 performance increase over the closest FP32, GPU-accelerated option, and almost ×3 performance advantage when compared with the INT8-quantized, TPU-accelerated implementation. More noticeably, this is achieved even when high-level synthesis (HLS) tools are used and no custom accelerators are developed. At the same time, the inherent reconfigurability of FPGAs opens a new field for their use as enabler hardware in RIS applications.

Comparative analysis and FPGA realization of different control synchronization approaches for chaos-based secured communication systems.

Synchronization of the chaotic systems has attracted much attention in recent years due to its vital applications in secured communication systems. In this paper, an implementation and comparative analysis of two different control approaches for synchronization between two identical four-dimensional hyperchaotic systems is presented. The two control approaches are the Adaptive nonlinear controller and the linear optimal quadratic regulator LQR. To demonstrate the effectiveness of each controller, the numerical simulation is presented using Matlab/Simulink and the control law is derived. The performance of the proposed controllers is compared based on four factors; response time, squared error integration, energy applied from the controller, and cost function. To measure the robustness of the control approaches, the performance factors are compared when there is a change in system parameters and a variation in the initial conditions. Then the proposed synchronization methods are implemented on the FPGA platform to demonstrate the utilized resources on Field Programmable Gate Array (FPGA) hardware platform and the operation speed. Finally, to generalize the results of the comparison, the study is implemented for the synchronization of another secured communication system consisting of two identical three-dimensional chaotic. The experimental results show that the LQR method is more effective than the Adaptive controller based on the performance factors we propose. Moreover, the LQR is much simpler to implement on hardware and requires fewer resources on the FPGA.