Field Programmable Gate Array Hardware Research Articles

An efficient controller-based architecture for AES algorithm using FPGA

An efficient controller-based architecture for AES algorithm using FPGA

Electromagnetic radiation control for nonlinear dynamics of Hopfield neural networks.

Electromagnetic radiation (EMR) affects the dynamical behavior of the nervous system, and appropriate EMR helps to study the dynamic mechanism of the nervous system. This paper uses a sophisticated four-dimensional Hopfield neural network (HNN) model augmented with one or more memristors to simulate the effects of EMR. We focus on the chaotic dynamics of HNN under the influence of EMR. Complex dynamical behaviors are found and transient chaotic phenomena have the same initial value sensitivity, showing how transient chaos is affected by EMR. Multiperiodic phenomena induced by quasi-periodic alternations are found in the dual EMR, as well as the suppression properties of the dual EMR for system chaos. This implies that the dynamical behavior of the HNN system can be controlled by varying the amount of EMR or the number of affected neurons in the HNN. Finally, a strong validation of our proposed model is provided by Multisim and Field Programmable Gate Array(FPGA) hardware.

Low latency optical-based mode tracking with machine learning deployed on FPGAs on a tokamak.

Active feedback control in magnetic confinement fusion devices is desirable to mitigate plasma instabilities and enable robust operation. Optical high-speed cameras provide a powerful, non-invasive diagnostic and can be suitable for these applications. In this study, we process high-speed camera data, at rates exceeding 100 kfps, on in situ field-programmable gate array (FPGA) hardware to track magnetohydrodynamic (MHD) mode evolution and generate control signals in real time. Our system utilizes a convolutional neural network (CNN) model, which predicts the n = 1 MHD mode amplitude and phase using camera images with better accuracy than other tested non-deep-learning-based methods. By implementing this model directly within the standard FPGA readout hardware of the high-speed camera diagnostic, our mode tracking system achieves a total trigger-to-output latency of 17.6 μs and a throughput of up to 120 kfps. This study at the High Beta Tokamak-Extended Pulse (HBT-EP) experiment demonstrates an FPGA-based high-speed camera data acquisition and processing system, enabling application in real-time machine-learning-based tokamak diagnostic and control as well as potential applications in other scientific domains.

Design and Hardware Implementation of CNN-GCN Model for Skeleton-Based Human Action Recognition

Deep learning algorithms in general have shown outstanding performances on tasks involving Human Action Recognition and spatio-temporal modeling. In our ever-more interconnected world where mobile and edge devices take center stage, there is a growing need for algorithms to operate directly on embedded platforms. Field-Programmable Gate Arrays (FPGA), owing to their reprogrammable nature and low-power attributes, stand out as excellent choices for these edge computing applications. In this work, our aims are threefold. Firstly, we aim to design and develop a novel custom model that combines Convolutional Neural Networks (CNNs) and Graph Convolutional Networks (GCNs) to effectively capture spatial and temporal features from skeleton data to achieve Human Action Recognition. Secondly, we endeavor to implement this custom model onto FPGA hardware using Vitis-AI, thus exploring the potential for efficient hardware acceleration of deep learning models. Lastly, we seek to evaluate the real-time performance of the FPGA-accelerated model in comparison to CPU and GPU implementations, assessing its suitability for deployment in real-world applications requiring low-latency inference. Experimental results based on the NTU dataset demonstrate the efficiency and accuracy of our custom model compared to traditional CPU or GPU implementations.

A brain machine interface framework for exploring proactive control of smart environments

Brain machine interfaces (BMIs) can substantially improve the quality of life of elderly or disabled people. However, performing complex action sequences with a BMI system is onerous because it requires issuing commands sequentially. Fundamentally different from this, we have designed a BMI system that reads out mental planning activity and issues commands in a proactive manner. To demonstrate this, we recorded brain activity from freely-moving monkeys performing an instructed task and decoded it with an energy-efficient, small and mobile field-programmable gate array hardware decoder triggering real-time action execution on smart devices. Core of this is an adaptive decoding algorithm that can compensate for the day-by-day neuronal signal fluctuations with minimal re-calibration effort. We show that open-loop planning-ahead control is possible using signals from primary and pre-motor areas leading to significant time-gain in the execution of action sequences. This novel approach provides, thus, a stepping stone towards improved and more humane control of different smart environments with mobile brain machine interfaces.

End-to-end codesign of Hessian-aware quantized neural networks for FPGAs

We develop an end-to-end workflow for the training and implementation of co-designed neural networks (NNs) for efficient field-programmable gate array (FPGA) hardware. Our approach leverages Hessian-aware quantization (HAWQ) of NNs, the Quantized Open Neural Network Exchange (QONNX) intermediate representation, and the hls4ml tool flow for transpiling NNs into FPGA firmware. This makes efficient NN implementations in hardware accessible to nonexperts, in a single open-sourced workflow that can be deployed for real-time machine-learning applications in a wide range of scientific and industrial settings. We demonstrate the workflow in a particle physics application involving trigger decisions that must operate at the 40 MHz collision rate of the CERN Large Hadron Collider (LHC). Given the high collision rate, all data processing must be implemented on FPGA hardware within the strict area and latency requirements. Based on these constraints, we implement an optimized mixed-precision NN classifier for high-momentum particle jets in simulated LHC proton-proton collisions.

Adaptive neuro fuzzy technology to enhance PID performances within VCA for grid-connected wind system under nonlinear behaviors: FPGA hardware implementation

Wind Energy Conversion Systems (WECSs) exhibit nonlinear behavior due to internal and external disturbances, which can significantly impact the control performance. Firstly, this paper proposes a Vector Control Approach (VCA) based on Adaptive Neuro Fuzzy (ANF) of Proportional Integral Derivative (PID) controllers for a variable speed Permanent Magnet Synchronous Generator (PMSG)-based WECS connected to the grid to address these issues. The proposed ANF-PID controller combines the robustness of the fuzzy logic with the neural network's performance to ensure high accuracy, excellent tracking, and robustness against the WECS's nonlinear behavior. The neural network automates the placement of fuzzy logic membership functions. Secondly, this paper suggests a real-time hardware implementation of the VCA based on ANF-PID using a Field Programmable Gate Array (FPGA) to reduce the processing time and the WECS's sampling period. The effectiveness of the VCA based on ANF-PID controllers is validated by conducting a numerical simulation within the Matlab-Simulink using the Xilinx System Generator tool, alongside an experimental in-the-loop hardware implementation using FPGA board. Different scenarios are conducted to validate the robustness and stability of the proposed VCA based on ANF-PID control schemes, which is compared to Conventional Fuzzy PID (C-FPID) and PID controllers. The results exhibit that the VCA based on ANF-PID controllers outperforms VCA-C-FPID and VCA-PID controllers in terms of precision, tracking accuracy, and robustness against the WECS's nonlinear behavior and the PMSG parameter variations. The performances of the proposed controllers are tested under some criteria. In fact, the proposed ANF-PID controller provides a Mean Absolute Error (MAE), a Mean Squared Error (MSE) and a Root Mean Squared Error (RMSE) of 8.1911 × 10−04, 8.4181 × 10−05 and 0.0092, respectively. Compared to the C-FPID controller, the proposed controller offers an improvement gain of 98.96 %, 99.61 %, and 93.79 % of MAE, MSE, and RMSE, respectively. When compared to the PID controller, its improvement is even more significant, with a reduction of 99.9919 %, 99.9999 %, and 99.9288 % of MAE, MSE, and RMSE, respectively. In addition, the ANF-PID-based VCA utilizes hardware resources on the FPGA efficiently, requiring only 65.60 % slices LUT, 0.28 % LUTRAM, and 22.99 % FF. This makes it a more cost-effective option compared to the VCA-C-FPID controller for diverse control systems.

FPGA-base object tracking: integrating deep learning and sensor fusion with Kalman filter

This research presents an integrated approach for object detection and tracking in autonomous perception systems, combining deep learning techniques for object detection with sensor fusion and field programmable gate array (FPGA-based) hardware implementation of the Kalman filter. This approach is suitable for applications like autonomous vehicles, robotics, and augmented reality. The study explores the seamless integration of pre-trained deep learning models, sensor data from a depth camera, real-sense D435, and FPGA-based Kalman filtering to achieve robust and accurate 3D position and 2D size estimation of tracked objects while maintaining low latency. The object detection and feature extraction are implemented on a central processing unit (CPU), and the Kalman filter sensor fusion with universal asynchronous receiver transmitter (UART) communication is implemented on a Basys 3 FPGA board that performs 8 times faster compared to the software approach. The experimental result provides the hardware resource utilization of about 29% of look-up tables, 6% of lookup table RAMs (LUTRAM), 15% of Flip-flops, 32% of Block-RAM, 38% of DSP blocks operating at 100 MHz, and 230400 baud rates for the UART. The whole FPGA design executes at 2.1 milliseconds, the Kalman filter executes at 240 microseconds, and the UART at 1.86 milliseconds.

Optimizing Neural Network Inference in Edge Robotics by Harnessing FPGA Hardware Acceleration

This research explores advancements in neural network inference for edge robotics through the implementation of hardware acceleration using Field-Programmable Gate Arrays (FPGA). Leveraging FPGA's versatility in custom hardware design, the research optimizes performance and energy efficiency by utilizing features such as Digital Signal Processors (DSP), Multiply-Accumulate (MAC) arrays, parallel processing units, Convolutional Neural Networks (CNN), and custom accelerators. The computational power of FPGA-based architectures is harnessed to significantly enhance the speed and efficiency of neural network inference tasks in edge robotics applications. Key aspects include the utilization of DSP blocks for efficient signal processing, MAC arrays for high-speed matrix operations crucial in neural network computations, and parallel processing units for concurrent execution of multiple tasks, improving overall system throughput. The integration of CNN directly onto FPGA hardware allows for minimal-latency inference, making it ideal for real-time applications in edge robotics scenarios. Custom accelerators tailored to specific neural network operations further optimize performance and resource utilization. The research involves the meticulous design and synthesis of hardware modules tailored to the target FPGA platform. Through rigorous optimization and parallelization techniques, the goal is to maximize resource utilization while minimizing latency and power consumption. The experimental findings showcase remarkable results, including a substantial increase in throughput, with values reaching up to 150 images/sec, and impressive accuracy rates exceeding 95% in classification tasks.

Radar-Jamming Decision-Making Based on Improved Q-Learning and FPGA Hardware Implementation

In contemporary warfare, radar countermeasures have become multifunctional and intelligent, rendering the conventional jamming method and platform unsuitable for the modern radar countermeasures battlefield due to their limited efficiency. Reinforcement learning has been proven to be a practical solution for cognitive jamming decision-making in the cognitive electronic warfare. In this paper, we proposed a radar-jamming decision-making algorithm based on an improved Q-Learning algorithm. This improved Q-Learning algorithm ameliorated the problem of overestimating the Q-value that exists in the Q-Learning algorithm by introducing a second Q-table. At the same time, we performed a comprehensive design and implementation based on the classical Q-Learning algorithm, deploying it to a Field Programmable Gate Array (FPGA) hardware. We decomposed the implementation of the reinforcement learning algorithm into individual steps and described each step using a hardware description language. Then, the reinforcement learning algorithm can be computed on FPGA by linking the logic modules with valid signals. Experiments show that the proposed Q-Learning algorithm obtains considerable improvement in performance over the classical Q-Learning algorithm. Additionally, they confirm that the FPGA hardware can achieve great efficiency improvement on the radar-jamming decision-making algorithm implementation.

Memory-Based Self-Ordering FFT for Efficient I/O Scheduling

A complex-valued self-ordering radix-2 memory-based Fast Fourier Transform (FFT) architecture suitable for low end Field Programmable Gate Arrays (FPGA) is presented. Employing a self-ordering algorithm within the data flow, both input and output data are kept in normal sequential order, not in digit-reversed-order. This way, with an appropriate scheduling, last stage of the FFT and I/O operations are performed in parallel with no wait states. Self-ordering FFT algorithms are generally designed for software implementations. We designed and implemented one on FPGA (hardware), showing that considerable number of clock cycle savings can be obtained compared to unordered FFT counterparts. The approach is implemented on various FPGAs. The results are compared with similar radix-2 architectures in terms of required clock cycles and resource usage, confirming the advantage of the approach.

Silicon spin qubit noise characterization using real-time feedback protocols and wavelet analysis

Recently, several groups have demonstrated two-qubit gate fidelities in semiconductor spin qubit systems above 99%. Achieving this regime of fault-tolerant compatible high fidelities is nontrivial and requires exquisite stability and precise control over the different qubit parameters over an extended period of time. This motivates the search for the efficient calibration of qubit control parameters against different sources of micro- and macroscopic noise and methods for noise analysis. Here, we present several single- and two-qubit parameter feedback protocols, optimized for and implemented in the state-of-the-art fast field-programmable gate array hardware. Furthermore, we present a wavelet-based analysis on feedback data collected over a ∼9 h time frame to gain insight into the different sources of noise in the system. Scalable feedback is an outstanding challenge and the presented implementation and analysis gives insight into the benefits and drawbacks of qubit parameter feedback, as feedback related overhead increases. This work demonstrates a pathway toward robust qubit parameter feedback and systematic noise analysis, crucial for mitigation strategies toward systematic high-fidelity qubit operation compatible with quantum error correction protocols.

Adaptive neural acceleration unit based on heterogeneous multicore hardware architecture FPGA and software-defined hardware

ABSTRACT This study is anchored in a heterogeneous multicore hardware architecture, specifically Field Programmable Gate Arrays (FPGAs), and software-defined hardware. It employs dynamic planning for the reconfiguration of a software-defined System-on-Chip (SOC) to expedite neural network processes. The reconfigured software-defined SOC serves as an efficient data processor, facilitating the hybrid development and verification of domain-specific System-on-Chip architectures, adhering to the Advanced Microcontroller Bus Architecture (AMBA) standard. The proposed block data trimming methodology significantly enhances overall hybrid computing efficiency by mitigating throughput limitations inherent in Systolic array hardware. The designed Systolic array Matrix Multiply Unit (MMU) is evaluated for a maximum MMU size of 32 × 32 and 1,024 Multiply Accumulator (MAC) units. Hybrid dynamic circuits are devised for the synthesis of int8, int16, int32, and int64 data types and associated logic circuits to validate the performance of parallel computing. It is anticipated that this proposed system can find utility in the development and deployment of unmanned devices, as well as in the integration of deep learning and multi-sensory fusion involving acoustic, tactile, and force sensory components.

Comparative analysis and FPGA realization of different control synchronization approaches for chaos-based secured communication systems.

Synchronization of the chaotic systems has attracted much attention in recent years due to its vital applications in secured communication systems. In this paper, an implementation and comparative analysis of two different control approaches for synchronization between two identical four-dimensional hyperchaotic systems is presented. The two control approaches are the Adaptive nonlinear controller and the linear optimal quadratic regulator LQR. To demonstrate the effectiveness of each controller, the numerical simulation is presented using Matlab/Simulink and the control law is derived. The performance of the proposed controllers is compared based on four factors; response time, squared error integration, energy applied from the controller, and cost function. To measure the robustness of the control approaches, the performance factors are compared when there is a change in system parameters and a variation in the initial conditions. Then the proposed synchronization methods are implemented on the FPGA platform to demonstrate the utilized resources on Field Programmable Gate Array (FPGA) hardware platform and the operation speed. Finally, to generalize the results of the comparison, the study is implemented for the synchronization of another secured communication system consisting of two identical three-dimensional chaotic. The experimental results show that the LQR method is more effective than the Adaptive controller based on the performance factors we propose. Moreover, the LQR is much simpler to implement on hardware and requires fewer resources on the FPGA.

Research on Measuring System of Sodium Hydroxide Concentration in Impregnation Solution Based on Ultrasonic Velocity Method

A sound velocity measurement system based on FPGA was designed. The time of flight was calculated by using the wave crest of ultrasonic signal to achieve high precision measurement of sound velocity. The high-speed data communication between field programmable gate array (FPGA) and host computer system is realized by using AN9238, DPRAM and 485 communication port. On the basis of FPGA hardware, high-speed AD chip is used for sampling to complete data storage and processing. The experimental results show that compared with the standard system, the time-of-flight measurement accuracy of the designed system is 0.1㎲, and the measurement accuracy of the solution sound velocity is better than 2 m/s, which verifies the reliability of the scheme.

Research on dynamic polarization control in continuous variable quantum key distribution systems

In a commercial fiber-based quantum key distribution system, the local and signal optical fields are transmitted through long distance fibers by using time division multiplexing and polarization multiplexing. The state of polarization of the optical field is inevitably disturbed by random birefringence of the standard single-mode fiber caused by external complex environments. This drift of the state of polarization significantly affects the balanced homodyne detection results and the secret key rate. Therefore, the key technology of the dynamic polarization control unit is crucial for the system in a large-scale commercial application. We theoretically analyze and prove that the polarization control unit only needs the combination of two degrees of freedom when considering the result of an arbitrary polarization extinction ratio at the receiver of the system. To overcome the influence of polarization variations, we propose a chaotic monkey algorithm based on Bayesian parameter estimation method and implement intelligence algorithm on field programmable gate array (FPGA) hardware under pulsed light with an integral-type detector for the dynamic polarization control unit. The simulation results show that the optimal combination is four degrees of freedom and the optimal prior distribution is an exponential distribution among various distributions in the dynamic polarization control unit. According to the simulation results, the experimental results show that the achieved polarization extinction ratio is over 30 dB and the average time of polarization control is 400 μs for a single random polarization scrambling. By combining the dynamic polarization control unit with the system, we demonstrate the continuous variable quantum key distribution (CV-QKD) under a continuous polarization scrambling scope of 0－2 krad/s and verify its effectiveness. In addition, the methods presented will improve the performance of the system and expand the range of applications even under strong external disturbance.

The switching and learning behavior of an octopus cell implemented on FPGA.

A dendrocentric backpropagation spike timing-dependent plasticity learning rule has been derived based on temporal logic for a single octopus neuron. It receives parallel spike trains and collectively adjusts its synaptic weights in the range [0, 1] during training. After the training phase, it spikes in reaction to event signaling input patterns in sensory streams. The learning and switching behavior of the octopus cell has been implemented in field-programmable gate array (FPGA) hardware. The application in an FPGA is described and the proof of concept for its application in hardware that was obtained by feeding it with spike cochleagrams is given; also, it is verified by performing a comparison with the pre-computed standard software simulation results.

A modified MixColumn-InversMixColumn in AES algorithm suitable for hardware implementation using FPGA device

This article described the Advanced Encryption Standard (AES) encryption and decryption process without using lookup tables in the MixColumns transformation and parallelizing the transformation process implemented in the Field Programmable Gate Array (FPGA) hardware. Parallelism of the hardware process conducted to the transformation of key schedule, addroundkey, subbyte and shiftrows (subshift) and mixcolumns in the first 5 rounds of the encryption process. The decryption process was parallelized in subshift transformations, both transformations were implemented at the same time. This research produced a modified AES encryption and decryption method and algorithm with the aim of minimizing the resources required for hardware implementation. The method in this article was applied to Xilinx ISE 14.7 software. The experimental results showed that the encryption process required 2,357 slice LUT's, 845 occupied slices and 26 IOB's, while the decryption process required 2,896 LUT's, 1,323 occupied slices and 26 IOB's resources. The encryption and decryption processes each took an average of 2.891 nanoseconds and 3.467 nanoseconds for every 128 bits of data. This approach leads us to obtain a component with minimum resources and enough computational speed.

Real-Time Synchronous Acquisition and Processing of Signal in Coherent Doppler Wind Lidar Using FPGA

Coherent Doppler wind lidar has become a primary remote sensing technique for measuring atmospheric wind fields in recent years. However, the high bandwidth of the time domain echo signal has limited real-time data acquisition and processing. In this work, we propose a real-time data acquisition and preprocessing integrated solution. This approach is implemented using on-chip system field programmable gate array (FPGA) hardware while utilizing a 7-channel base-4 polyphase fast Fourier transform calculation module and a pipelined structure operation. Within a 1 s data collection time, the real-time rapid acquisition and spectral preprocessing of lidar echo signals at a range of 9.9 km can be achieved. We compare the observation data with the measurement data from Windcube100s and radiosondes, and the results indicate that the coherent wind lidar developed in this paper can detect heights above 4.0 km, with effective data acquisition rates of 82% and 61% in the height ranges of 1500–2000 m and 2000–2500 m, respectively. At the height range of 3.5 km, the correlations for horizontal wind speed and direction measured by the lidar were all above 0.99, with the wind speed and direction measurement deviations being better than 0.56 m/s and 8.40∘, respectively.

AutoMLP: A Framework for the Acceleration of Multi-Layer Perceptron Models on FPGAs for Real-Time Atrial Fibrillation Disease Detection.

Cardiovascular diseases are a leading cause of death globally, and atrial fibrillation (AF) is a common arrhythmia that affects many people. Detecting AF in real-time using hardware acceleration can prompt timely medical intervention. Multi-layer perceptron (MLP) has demonstrated the ability to detect AF accurately. However, implementing MLP on Field-Programmable Gate Array (FPGA) for real-time detection poses challenges due to the complex hardware design requirements. This study presents a novel framework for generating hardware accelerators to detect AF in real-time using MLP on FPGA. The framework automates evaluating MLP model topology, data type, and bit-widths to generate parallel acceleration. The generated solutions are evaluated using two AF datasets, PhysioNet MIT-BIH atrial fibrillation (AFDB) and China Physiological Signal Challenge 2018 (CPSC2018), regarding execution time, resource utilization, and accuracy. The evaluation results demonstrate that the hardware MLP can achieve a speedup higher than 1500× and around 25000× lower energy consumption than an embedded CPU. These satisfactory results prove the framework's suitability and convenience for the online detection of AF in an accelerated and automatic way through FPGA hardware implementation.