Field Programmable Gate Array Core Research Articles

A control hardware based on a field programmable gate array for experiments in atomic physics.

Experiments in Atomic, Molecular, and Optical (AMO) physics require precise and accurate control of digital, analog, and radio frequency (RF) signals. We present control hardware based on a field programmable gate array core that drives various modules via a simple interface bus. The system supports an operating frequency of 10 MHz and a memory depth of 8 M (223) instructions, both easily scalable. Successive experimental sequences can be stacked with no dead time and synchronized with external events at any instructions. Two or more units can be cascaded and synchronized to a common clock, a feature useful to operate large experimental setups in a modular way.

High Performance Reversible Direct Data Synthesizer for Radio Frequency Applications

Design of Reversible logic gate enabled Reconfigurable Direct digital synthesizer is evaluated here. The need for Direct Digital Synthesizers (DDS) inherently finds application in the area of radio frequency communication. DDS is a method of producing an analog waveform—usually a sine wave—by generating a time-varying signal in digital form and then performing a digital-to-analog conversion. The proposed design presents an important analysis based on Reversible logic gates for the application of DDS which is a powerful device employed to produce standard signal sweeps from lowest frequency to highest frequency. The sweeps of DDS frequency depends on the configurable frequency words produced by high speed Field Programmable Gate Array (FPGA) platforms. Because operations within DDS devices are primarily digital, it can offer fast switching between output frequencies, fine frequency resolution, and operation over a broad spectrum of frequencies. With advances in design and process technology, today’s DDS devices are very compact and draw little power. Here the proposed system focuses on development of DDS through Artificial Intelligence (AI) with Field Programmable Gate Array (FPGA) devices. The primary need for FPGA and AI combination provides the replacement of analog Phase Locked Loop (PLL) in traditional DDS circuits. The fully digital architecture enable the system able to configure the digital PLL developed inside the FPGA core. Low noise and Low power factor is being achieved through low power techniques utilized in the architecture development part. The proposed system increase the sweep frequency resolution, Reverse fluctuations through leakage voltage etc.

Frequency-Domain Power Delivery Network Self-Characterization in FPGAs for Improved System Reliability

Modern field-programmable gate arrays (FPGAs) operate at a core voltage around 1 V and therefore even small voltage fluctuations lead to timing violations and logic errors. The power delivery network (PDN) between the voltage regulator and the FPGA core must be carefully designed to achieve a low output impedance over a broad range of frequencies. Simulation tools are commonly used to estimate the impedance, however, they do not account for aging, component variations, and inaccurate modeling of parasitic elements, all of which lead to PDN design deviation. In this paper, two schemes are presented: first, to extract the dc resistance in the power delivery path, and second, to identify the high impedance frequency band(s) in the PDN. The embedded impedance extraction tool is synthesized within the FPGA load, in coordination with a mixed-signal current-mode dc–dc converter. A new self-calibrated carry-chain-based analog-to-digital converter (CC-ADC) is used for high-speed sampling of the core voltage. The proposed schemes are demonstrated on an Intel Cyclone IV FPGA board. Real-time IR -drop compensation is shown to eliminate logic errors in an finite impulse response filter application. It is also shown that the fail/pass map of a crossbar application matches well with the extracted impedance profile versus voltage and frequency. By modifying the PDN based on the extracted results, the voltage operating range and reliability of the crossbar application are greatly extended.

Robust Self-Calibrated Dynamic Voltage Scaling in FPGAs With Thermal and IR-Drop Compensation

Field programmable gate arrays (FPGAs) are widely used in telecom, medical, military, cloud computing, and other high-performance computing applications, thanks to their unique combination of parallel hardware execution and reprogrammability. During compilation, the computer-aided design (CAD) tool estimates the maximum operating frequency of the user application based on the worst case timing analysis of the critical path at a fixed nominal supply voltage, which usually results in significant voltage or frequency margin. Hence dynamic voltage scaling (DVS) has great potential to reduce the power overhead in FPGAs; however, the reprogrammability of FPGAs make a safe implementation of DVS for any application that could be programmed into the FPGA challenging. This work presents a robust universal DVS scheme for FPGAs intended to run on a system production line, or regularly during each FPGA power-up. The proposed scheme requires the FPGA to be programmed twice: offline self-calibration and online DVS. During the offline self-calibration, the FPGA frequency and core voltage operating limits at different self-imposed temperatures are automatically found and stored in a calibration table (CT). During online operation, the power stage refers to the CT and dynamically adjusts the core voltage according to the FPGA temperature and the resistive voltage drop in the power delivery path. The proposed DVS scheme is demonstrated on a 60-nm Intel Cyclone IV FPGA, with a digitally controlled dc–dc converter, leading to 40% power savings in two typical applications.

Multimed: An Integrated, Multi-Application Platform for the Real-Time Recording and Sub-Millisecond Processing of Biosignals.

Enhanced understanding and control of electrophysiology mechanisms are increasingly being hailed as key knowledge in the fields of modern biology and medicine. As more and more excitable cell mechanics are being investigated and exploited, the need for flexible electrophysiology setups becomes apparent. With that aim, we designed Multimed, which is a versatile hardware platform for the real-time recording and processing of biosignals. Digital processing in Multimed is an arrangement of generic processing units from a custom library. These can freely be rearranged to match the needs of the application. Embedded onto a Field Programmable Gate Array (FPGA), these modules utilize full-hardware signal processing to lower processing latency. It achieves constant latency, and sub-millisecond processing and decision-making on 64 channels. The FPGA core processing unit makes Multimed suitable as either a reconfigurable electrophysiology system or a prototyping platform for VLSI implantable medical devices. It is specifically designed for open- and closed-loop experiments and provides consistent feedback rules, well within biological microseconds timeframes. This paper presents the specifications and architecture of the Multimed system, then details the biosignal processing algorithms and their digital implementation. Finally, three applications utilizing Multimed in neuroscience and diabetes research are described. They demonstrate the system’s configurability, its multi-channel, real-time processing, and its feedback control capabilities.

Unified Communication Framework

The unified communication framework (UCF) is a unified network protocol and field programmable gate array core for high-speed serial interfaces employed in data acquisition systems. It provides up to 64 different communication channels via a single serial link. One channel is reserved for timing and trigger information, whereas the other channels can be used for slow control interfaces and data transmission. All channels except the timing are bidirectional and share network bandwidth according to assigned priority. The timing channel distributes messages with fixed and deterministic latency in one direction. In this regard, the protocol implementation is asymmetric. The precision of the timing channel is given by the jitter of the recovered clock and is typically in the order of 10–20 ps rms. The timing channel has highest priority and a slow control interface should use the second highest priority channel in order to avoid long delays due to high traffic on other channels. The framework supports point-to-point connections and starlike 1:n topologies for optical networks with a passive splitter. It always employs one of the connection parties as a master and the others as slaves. The starlike topology can be used for front ends with low data rates or pure time distribution systems. In this case, the master broadcasts information according to assigned priority, whereas the slaves communicate in a time sharing manner to the master. In the open systems interconnection layer model, the UCF can be classified as layers one to three, which includes the physical, the data, and the network layer.

High resolution time-to-digital converter (TDC) implemented in field programmable gate array (FPGA) with compensated process voltage and temperature (PVT) variations

The paper presents and compares FPGA implementations of Time-to-Digital Converters (TDC) developed in the framework of the XNAP project, an international collaboration building Avalanche Photo Diode based area X-ray detectors. We are revisiting and presenting updated results achieved with recent components of two different TDC architectures previously described in the literature. Particularly care is given to optimize the Differential Non-Linearity (DNL) in order to obtain meaningful resolution figures that can be applied to the final applications. In the first implementation, based on a tapped delay line interpolator, the achieved resolution is in the 40–100ps range. The hardware compensation for process voltage and temperature (PVT) variations, a weak point of FPGA designs, has been fully addressed by developing specific circuitry. Our hardware design allows closing a feedback loop for controlling the FPGA core voltage. PVT variations are therefore compensated by hardware in real time. The second implementation, based on a multiple-phase clock interpolator, the resolution is close to 175ps. Interpolator DNL better than ±0.4 and ±0.2LSB could be achieved. The relative advantages of both architectures are discussed within the scope of the foreseen applications.

A low-power Wave Union TDC implemented in FPGA

A low-power time-to-digital convertor (TDC) for an application inside a vacuum has been implemented based on the Wave Union TDC scheme in a low-cost field-programmable gate array (FPGA) device. Bench top tests have shown that a time measurement resolution better than 30 ps (standard deviation of time differences between two channels) is achieved. Special firmware design practices are taken to reduce power consumption. The measurements indicate that with 32 channels fitting in the FPGA device, the power consumption on the FPGA core voltage is approximately 9.3 mW/channel and the total power consumption including both core and I/O banks is less than 27 mW/channel.

Feat Of Submerged Scheme Relevance In Power Pc Processor Based Fpga Using Fpga Ip Cores

Under water systems use processor based rooted systems to provide control and guidance to the under water vehicles. They obtain target and vehicle dynamics data from sensors and gyros, and process this data as per control and guidance algorithms to generate control and guidance parameters to the actuation system. Traditionally x86 families are being used in these systems in amassing to memory, I/Os and other peripherals being on the card. The recent developments in FPGA (Field Programmable Gate Array) technology has made pavement to use superior FPGAs with IP cores to develop under water systems. The modern FPGA devices include 32-bit Power PC processor, memory blocks and programmable area to comprise peripheral blocks. Under water systems developed out of the FPGA cores are definitely have several advantages like, saving the card size (FPGA accommodates several of the components in addition to the processor), flexibility to adopt changes in design (as FPGA can be programmed by the end user), preventing obsolescence of components. Building an under water systems based on FPGA IP cores is an innovative and hottest technological demonstration with several advantages to prophesy. The present work describes the dwindling in power consumption and size of the Under Water System. This work will also be productive to CSS Division of NSTL in designing and miniaturizing embedded systems such as MCS, MDAC etc. used in marine systems. The present work describes the mellowness of under water system relevance in Power PC Based FPGA using FPGA IP Cores. This work includes understanding the design flow of EDK and learns about various IP Cores Provided by Xilinx EDK 10.1. The underwater system application has been implemented in ‘C’ language by using Xilinx Device Drivers. A custom logic in VHDL has been developed for truncating extra bits of ADC. In Xilinx ISE10.1 project navigator the developed VHDL Code has been integrated with C. The combined bit file generated has been downloaded into Xilinx Virtex-II Pro FPGA Proto Board.

Impact of Power Supply Voltage Variations on FPGA-Based Digital Systems Performance

Power Supply Noise (PSN) may be induced by environmental or operational conditions, and has impact on digital systems performance. Field Programmable Gate Array (FPGA) vendors hide this effect, by offering more conservative performance specifications, so that users do not have to worry about it. The purpose of this paper is to characterize the impact of power supply voltage disturbances on signal propagation delays of digital circuits implemented in FPGA. Element and path propagation delay variation models for FPGAs are proposed, based on similar models previously proposed by the authors for ASIC designs. Model accuracy (in the order of 1 % deviation) is demonstrated by experimental results obtained with three FPGA development boards, using 65 nm FPGA devices. The proposed models allow designers to estimate the FPGA core supply voltage variation range for which correct functionality still holds, for a given operating clock frequency. Moreover, the proposed models can be used to implement time borrowing techniques in FPGA-based designs, by identifying signal critical paths and delaying signal capture in memory elements terminating the longest paths.

Iterative-Gradient Based Complex Divider FPGA Core with Dynamic Configurability of Accuracy and Throughput

A field programmable gate array (FPGA) implementation of a highly configurable complex divider is presented, based on an iterative gradient algorithm. The proposed architecture allows to configure both the accuracy and the throughput of the division operation, which makes it suitable for diverse applications with different requirements. Results show how various throughputs can be achieved under different maximum error and iteration limit configurations. Besides, the resource occupation is considerably small, compared with previous solutions.

A 90-nm Low-Power FPGA for Battery-Powered Applications

Programmable logic devices such as field-programmable gate arrays (FPGAs) are useful for a wide range of applications. However, FPGAs are not commonly used in battery-powered applications because they consume more power than application-specified integrated circuits and lack power management features. In this paper, we describe the design and implementation of Pika, a low-power FPGA core targeting battery-powered applications. Our design is based on a commercial low-cost FPGA and achieves substantial power savings through a series of power optimizations. The resulting architecture is compatible with existing commercial design tools. The implementation is done in a 90-nm triple-oxide CMOS process. Compared to the baseline design, Pika consumes 46% less active power and 99% less standby power. Furthermore, it retains circuit and configuration state during standby mode and wakes up from standby mode in approximately 100 ns

Mapping a Sensor Interface and a Reconfigurable Communication System to an FPGA Core

In this short communication, we present a novel approach for integrating a standard sensor interface and a reconfigurable wireless data communication channel on a single Field Programmable Gate Array (FPGA) chip. In a traditional wireless sensor device, sensor and communication electronics are built as separate components and their integration consists of designing a board to accommodate multiple integrated circuits (ICs). In contrast, the FPGA core allows us to put a standard I²C sensor interface, embedded Digital Signal Processing (DSP) algorithms for Software-Defined Radio (SDR), and a microprocessor control system on a singlechip reconfigurable device. In our experimental FPGA-based sensor platform, the I²C interface is used both to receive data from the temperature sensor and to control the analog Radio Frequency (RF) transceiver board. Amplitude Shift Keying (ASK) modulation and demodulation are implemented using DSP techniques within an SDR framework, and the microprocessor system is used to read sensor data and control various components. The prototype design was deployed on a Nallatech development board containing a Xilinx Virtex 2V3000 FPGA chip and was successfully tested with Dallas Semiconductor DS1721 digital temperature sensor. One instance of the prototype transmitted the temperature red by the sensor while second instance acted upon the received over the air temperature readings by turning LED on or off.