Field Oxide Research Articles

Modeling and Characterization of the Narrow-Width Effect of 4H-SiC MOSFETs With Local Oxidation of SiC Isolation

In this article, the narrow-width effect (NWE) of 4H-SiC MOSFETs with local oxidation of SiC (LOCOSiC) isolation is reported. A channel width-dependent current hump was observed in the subthreshold region for n-type 4H-SiC MOSFETs with LOCOSiC, and a channel width-dependent threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V} _{th}$ </tex-math></inline-formula> ) shift was observed for p-type 4H-SiC MOSFETs with LOCOSiC. This unusual NWE arises from the increase in the gate oxide thickness from the channel center toward the isolation edge and is different from the conventional NWE found in local oxidation of silicon (LOCOS) technology, which arises from the charge stored in the parasitic field oxide (FOX) capacitor and lateral dopant encroachment. A H2O diffusion and oxidation model is proposed in this article to explain the growth of a long bird’s beak in 4H-SiC MOSFETs with LOCOSiC. Technology computer-aided design (TCAD) simulations were executed to explore the H2O diffusion behavior of these MOSFETs, and an analytical formula was derived to predict the oxide layer thickness and length of bird’s beak along the diffusion path in the H2O diffusion and oxidation model. The problems caused by the long bird’s beak and unusual NWE can be overcome by increasing the overetching time of the pad oxide removal and marginally decreasing the thickness of the FOX layer. Therefore, the NWE of the LOCOSiC isolation is expected to be weaker than that of the LOCOS isolation because field implantation is unnecessary, and thus, dopant encroachment does not occur in the LOCOSiC technology.

A Study on the Isolation Ability of LOCal Oxidation of SiC (LOCOSiC) for 4H-SiC CMOS Process

The oxidation rate of SiC can be greatly enhanced by pre-amorphization ion-implantation (PAI), and the PAI process has been employed to form the LOCal Oxidation of SiC (LOCOSiC) structure for device isolation in SiC integrated circuits (ICs). This work presents the study on the defect layer below the thermally grown SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and the impact of the defect layer on devices. The deep-level transient spectroscopy (DLTS) analysis reveals that the defect layer consists lots of C vacancies and Si vacancies. The leakage current of the edge-intensive N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /P-junction exhibits stronger temperature dependence than that of the P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /N-junction. This result confirms that C vacancy is an effective lifetime killer in n-type SiC, but not in p-type SiC. Although these defects increase the leakage current of the edge-intensive SiC N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> /P-junction by 42 times at 150 °C compared with the junction with conventional chemical vapor deposited (CVD) field oxide (FOX), the leakage current is still much lower than the required OFF-state current of ICs. The defect layer has high resistance, and it is hard to let the SiC surface into inversion state so that the threshold voltage of the field MOSFET is higher than ±24 V.

Total-Ionizing-Dose Radiation-Induced Dual-Channel Leakage Current at Unclosed Edge Termination for High Voltage SOI LDMOS

Total-ionizing-dose (TID) radiation response on unclosed edge termination is investigated for high voltage silicon-on-insulator (SOI) laterally diffused metal-oxide-semiconductor (LDMOS) in this article. Radiation-induced dual-channel leakage current model is proposed to reveal the mechanism of leakage current generation at OFF-state. Radiation causes a mass of positive oxide trapped charges generated in field oxide (FOX) layer and buried oxide layer. Owing to the P-SOI layer with significantly low doping concentration, two inversion channels are formed at the surface and bottom in the edge termination region, which provides parallel conduction paths. Electrons from the source N+ are pulled down and flow along the bottom channel while punchthrough occurring. The radiation-induced leakage current could be suppressed by thinning FOX layer, increasing the doping concentration of the P-SOI layer, and thickening the SOI layer.

Experimental investigation on total-ionizing-dose radiation effects on the electrical properties of SOI-LIGBT

In this paper, the experimental investigation on the electrical properties of silicon-on-insulator lateral insulated-gate bipolar transistor (SOI-LIGBT) after total-ionizing-dose (TID) irradiation is presented. We find that the TID irradiation reduces the threshold voltage (Vth), and increases the collector current (ICE) at the same gate voltage (Vg). The raising ICE is mainly attributed to the negative shift of the Vth. However, at the same overdrive voltage (Vov = Vg − Vth), the ICE at small VCE increases and the ICE at high VCE decreases after irradiation. The distinctive response of the out-put characteristics after irradiation is ascribed to the positive trapped charges in the field oxide (FOX) layer and the buried oxide (BOX) layer. The inimitable out-put behavior occurs at whatever the sign of the gate bias voltage during irradiation. The degradation mechanisms of the TID effects on the SOI-LIGBT are further analyzed and confirmed by simulation.

TID-Induced OFF-State Leakage Current in Partially Radiation-Hardened SOI LDMOS

The electrical characteristics of silicon-on-insulator (SOI) n-channel laterally diffused metal oxide semiconductor field effect transistors (NLDMOSFETs) are examined after exposure to the total ionizing dose (TID). The devices are partially radiation hardened in that the gate oxide (GOX) and the field oxide (FOX) have undergone a hardening process, but not the buried oxide (BOX). Two bias conditions, OFF-state and all terminals grounded, during irradiation are examined. The irradiated device shows that the OFF-state leakage current ( $I_{L}$ ) of these devices increases with the accumulated dose. The physical mechanisms for the $I_{L}$ are analyzed by technology computer-aided design (TCAD) simulation. The OFF-state leakage current ( $I_{L}$ ) can be explained due to the effects of radiation-induced trapped charge at the BOX silicon interface.

Robust reliability and electrical performances by the bulk-contact modulation in 60-V p-channel LDMOS power components

ABSTRACTTo increase reliability and electrical performance, shallow-trench isolation (STI) (or called field-oxide (FOX)) structures were inserted in the bulk-contact region of 60-V high-voltage p-channel lateral-diffused MOSFET (pLDMOS) devices in this study. As the FOX ratio increased with the addition of FOX segments, the value of the secondary breakdown current (It2) was enhanced. Therefore, the anti-electrostatic discharge ability of a pLDMOS device can be efficiently improved using this novel method. In addition, when the weighting ratio of FOX structures increased, variation values in the trigger voltage (Vt1) and holding voltage (Vh) of the corresponding samples remained within the range of approximately 1–4 V. The Ron value decreased because of more uniform conduction. The experimental data for the FOX structures added to the bulk revealed that the It2 value was improved by approximately 13.98%, Vh values were greater than 60 V (which is favorable for latch-up immunity), and the Ron value was decreased by approximately 12.62% compared with a reference device under test (without FOX segments in the bulk-contact region).

A Four-FET Method for Extracting Mobility in FETs Without Field Oxide

Many fabricated III-V MOSFETs have electrically thin field oxide (FOX) that leads to parasitic currents and parasitic capacitances. When extracting long-channel mobility of such devices using the conventional two-FET method, some of these parasitic components are not subtracted out. In this paper, we present a simple four-FET method for extracting long-channel mobility that works well even when the equivalent oxide thickness (EOT) of the FOX is equal to the EOT of the FET gate oxide.

A 680 V LDMOS on a thin SOI with an improved field oxide structure and dual field plate

A 680 V LDMOS on a thin SOI with an improved field oxide (FOX) and dual field plate was studied experimentally. The FOX structure was formed by an “oxidation-etch-oxidation" process, which took much less time to form, and had a low protrusion profile. A polysilicon field plate extended to the FOX and a long metal field plate was used to improve the specific on-resistance. An optimized drift region implant for linear-gradient doping was adopted to achieve a uniform lateral electric field. Using a SimBond SOI wafer with a 1.5 μm top silicon and a 3 μm buried oxide layer, CMOS compatible SOI LDMOS processes are designed and implemented successfully. The off-state breakdown voltage reached 680 V, and the specific on-resistance was 8.2 Ω·mm2.

Thermal Circuit for SOI MOSFET Structure Accounting for Nonisothermal Effects

An accurate thermal circuit model for 2-D silicon-on-insulator (SOI) MOSFETs is presented to account for nonisothermal effects. The circuit model is modified from an approach developed earlier for the temperature distribution in 2-D SOI MOSFETs. A generalized approach to establishing a nonisothermal circuit and its circuit elements is presented for different SOI structures, such as multidevices on a single island and multifinger structure. The developed circuit model is verified with the finite-element method (FEM) in different SOI structures, including a structure coupled with interconnects. Heat flow to the contacts, poly gate, and buried oxide (BOX)/field oxide (FOX) is examined. Heat exchange via FOX between neighboring islands is carefully investigated, as compared to the FEM. It is shown from the developed model and FEM simulations that heat exchange via FOX between two thin islands is negligible if the distance between the islands is near or greater than the island thickness plus the BOX thickness.

HDP-CVD STI oxide process with in situ post deposition laterally enhanced sputter etchback for the reduction of pattern-dependent film topography in deep submicron technologies

This paper introduces a postdeposition pattern-dependent topography-reduction enhancement to the high-density plasma chemical-vapor deposition (HDP-CVD)oxide profile for shallow trench isolation in deep submicron technologies. The enhancement is labeled "laterally enhanced sputter etchback" (L-SEB) and is carried out in situ in the HDP-CVD reactor after film deposition. The L-SEB is set up using O/sub 2/ and Ar at high O/sub 2/ flow. A design of experiment was run to search for optimum gas flow conditions. The optimized process is shown to yield significant lateral "pull-in" of the sizeable HDP oxide cones over large thin-oxide features and flattening of smaller cones over dense small features, without appreciable impact on field oxide (FOX) thickness or corner integrity. This contributes a significant improvement to an STI module that incorporates downstream planarization processes of reverse-tone etch (RTE) and chemical mechanical polishing (CMP). It also allows a start with a thinner film thickness and usage of a smaller lithography compensation factor for the reverse-tone mask, thus facilitating a smaller minimum feature for RTE exposure. These advantages enhance the manufacturability of the STI process module in terms of reducing the starting HDP film thickness,cutting down on etching and polishing times of RTE and CMP, respectively,and yielding better post-CMP within-die and within-wafer FOX uniformities.

Charge transport in thick SiO 2-based dielectric layers

Charge transport in thick (≥ 1 μm) SiO 2-based dielectric layers was investigated by means of I( U) measurements. Investigations were carried out on thermally grown field oxide (FOX) as well as on TEOS and BPSG. Gate oxide layers (GOX) were measured as reference. C( U) measurements were performed for the determination of charges in the oxide. To determine the electrical parameters of the layers, the model from Chen and Wu[1] was developed further. The model takes into account tunnelling, capture and emission processes, impact ionization, recombination, interface states and ohmic currents. The I( U) characteristics for all dielectrics examined can be described with the aid of the model. The FOX parameters correspond to those of GOX. The parameters of TEOS and BPSG fluctuate strongly with the process parameters. After high-temperature annealing and from measurement of the examined parameters, the insulation properties of TEOS and BPSG were found to be at least as good as those of FOX.

Radiation hard LOCOS field oxide

It is known that radiation hard field oxides (FOX) can be produced by combination of a thin thermal oxide and a thick P- or As-doped deposited oxide. The doping atoms serve as recombination centers and electron traps for radiation induced charges. This results in a distinctly lower oxide charge at the Si/SiO/sub 2/ interface compared to conventional thermal oxides and, therefore, higher radiation hardness. The radiation resistance of thermally grown FOX for LOCOS isolation cannot be improved much by changes in oxidation parameters. The newly developed radiation hard FOX is produced by local oxidation of P-doped poly-Si. This method preserves the advantages of the LOCOS technology. To distinguish this process from the regular LOCOS process we termed it LOPOX (Local Polysilicon Oxidation). Even with low doping concentrations radiation hardness is improved considerably compared to conventional thermal oxides.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>