Field Of Electronic Design Automation Research Articles

Monitoring the development trend and competition status of high technologies using patent analysis and bibliographic coupling: The case of electronic design automation technology

High technologies play an important role in social progress and economic growth. Monitoring the development trend and competition status of high technology is crucial for policymakers, managers, and developers. This study proposes a framework that integrating the analysis of technological evolutionary trends and competitive status, the results of which will be helpful for engineers and developers for technology scouting and forecasting, but also for policymakers and managers for research and development (R&D) strategy. The electronic design automation (EDA) technology is selected as a case study. The patent analysis and bibliographic coupling are used to analyze the overview and identify the critical technical areas of EDA technology. This research also identifies the competition status of the main competitors in the EDA field from three aspects, including the market and technology fields, R&D capability, and comprehensive evaluation of patents. Our results show that the United States has an absolute advantage in the competition status of EDA technology. This study contributes to monitoring the development situation and competition status of high technologies, and will be of interest to policymakers and engineers.

Progress of Tensor-Based High-Dimensional Uncertainty Quantification of Process Variations

Uncertainty quantification under process variations is an important topic in computational electromagnetics (EM) and electronic design automation (EDA). The popular stochastic methods become computationally inefficient when the number of uncertain parameters grows. A promising technique to address this challenge is tensor computation. This short paper reviews some recent tensor methods for high-dimensional uncertainty quantification in the field of EDA and computational EM.

SAT based solutions for detailed routing of island style FPGA architectures

Detailed routing solutions for island style FPGA architectures using Boolean satisfiability (SAT) based formulations have been proposed in this paper. Due to decreasing size of ICs and hence, the increasing complexity of the routing resource constraints, routing has been a big challenge in electronic design automation field. Our proposed techniques work on multi-pin net routing where all nets are considered for routing in their intact form whereas, most of the existing routing solutions decompose multi-pin nets into two-pin nets for detailed routing to ease the problem. However this approach, apart from increasing the number of nets in the circuits, may also introduce pin doglegging which, when not permitted by the architecture of FPGA, would require extra constraints to eliminate. Many detailed routers adopt sequential detailed routing approaches which are vulnerable to the net ordering problem which may cause a routable circuit to be erroneously classified as unroutable. Our proposed techniques avoid these pitfalls by keeping the multi-pin nets intact and solve all nets simultaneously using SAT. The SAT-based multi-pin net dogleg-free formulations presented here achieve significant improvement over existing SAT-based solutions with respect to the number of variables and clauses used, thereby achieving greater scalability and also display comparable and sometimes better routability results on benchmark circuits when compared with other detailed routing solutions. Detailed routing is also significantly affected by the architecture of the switching blocks. This paper proposes SAT-based formulation for three different switch box architectures i.e. Subset, Wilton, and Universal switches. Our experiments clearly demonstrate how routing solutions for a circuit can differ significantly for different types of switch boxes.

The Design Automation Conference and the Early Days of EDA

This paper is based on an invited talk presented at the 50th DAC. Using superb examples, it portrays the early days of Electronic Design Automation field and the formation of the Design Automation Conference.

Fully Dynamic Evaluation of Sequence Pair

In the electronic design automation field, as well as in other areas, problem instances and solutions are often subject to discrete changes. The foundational significance of efficient updates of the criterion value after dynamic updates, instead of recomputing it from scratch each time, has attracted a lot of research. In this paper, motivated by the significance of the sequence pair (SP) representation for floorplanning, we develop a fully dynamic algorithm of SP evaluation, that efficiently updates a criterion value after insertions and deletions of SP elements and after modifications of element weights. Our result is based on a new data structure for the predecessor problem, which maintains the whole history of its dynamic modifications, and the path-compression technique from the union-find problem, which efficiently support predecessor queries. Numerical experiments showed that our algorithm exhibits linear-time behavior and considerably reduces the time of SP evaluation, compared to other approaches.

Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis

Efficient utilization of the inherent parallelism of multi-core architectures is a grand challenge in the field of electronic design automation (EDA). One EDA algorithm associated with a high computational cost is automatic test pattern generation (ATPG). We present the ATPG tool TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully chosen mix of various optimization techniques, multi-million-gate industrial circuits are handled without aborts. TIGUAN supports both conventional single-stuck-at faults and sophisticated conditional multiple stuck-at faults which allows to generate patterns for non-standard fault models. We demonstrate how TIGUAN can be combined with conventional structural ATPG to extract full benefit of the intrinsic strengths of both approaches.

Computer-Aided Optimization of DNA Array Design and Manufacturing

DNA probe arrays, or DNA chips, have emerged as a core genomic technology that enables cost-effective gene expression monitoring, mutation detection, single nucleotide polymorphism analysis, and other genomic analyses. DNA chips are manufactured through a highly scalable process called very large-scale immobilized polymer synthesis (VLSIPS) that combines photolithographic technologies adapted from the semiconductor industry with combinatorial chemistry. Commercially available DNA chips contain more than half a million probes and are expected to exceed 100 million probes in the next generation. This paper is one of the first attempts to apply very large scale integration (VLSI) computer-aided design methods to the physical design of DNA chips, where the main objective is to minimize total border cost (i.e., the number of nucleotide mismatches between adjacent sites). By exploiting analogies between manufacturing processes for DNA arrays and for VLSI chips, the authors demonstrate the potential for transfer of methodologies from the 40-year-old field of electronic design automation to the newer DNA array design field. The main contributions of this paper are the following. First, it proposes several partitioning-based algorithms for DNA probe placement that improve solution quality by over 4% compared to best previously known methods. Second, it gives a new design flow for DNA arrays, which enhances current methodologies by adding flow awareness to each optimization step and introducing feedback loops. Third, it proposes solution methods for new formulations integrating multiple design steps, including probe selection, placement, and embedding. Finally, it introduces new techniques to experimentally evaluate the scalability and suboptimality of existing and newly proposed probe placement algorithms. Interestingly, the authors find that DNA placement algorithms appear to have better suboptimality properties than those recently reported for VLSI placement algorithms [C.C. Chang et al., Optimality and scalability study of existing placement algorithms, Proc. Asia South-Pacific Design Automation Conf., Kitakyushu, Japan, p.621-7, Jan. 2003; J. Cong et al., Optimality, scalability and stability study of partitioning and placement algorithms, Proc. Int. Symp. Physical Design (ISPD), Monterey, CA, p.88-94, 2003]

Keeping current with silicon and systems technology in the mid-90s

IEEE Design & Test Magazine was originally conceived in late 1982 to cover the nascent field of electronic design automation (EDA). Software tools to automate many parts of the IC design process were becoming essential to support the rapid growth of IC densities and to leverage IC capabilities. The magazine was one of the first nontrade engineering publications dedicated to educating professional engineers about state-of-the-art practices in silicon and systems technology. More than a decade later, its mission statement had evolved to "Make IEEE Design & Test the premiere professional magazine reporting on both innovative recent practice and promising future methods in design and test of electronics and electronics-based systems".

A new heuristic for rectilinear Steiner trees

The minimum rectilinear Steiner tree (RST) problem is one of the fundamental problems in the field of electronic design automation. The problem is NP-hard, and much work has been devoted to designing good heuristics and approximation algorithms; to date, the champion in solution quality among RST heuristics is the Batched Iterated 1-Steiner (BI1S) heuristic of Kahng and Robins. In a recent development, exact RST algorithms have witnessed spectacular progress: The new release of the GeoSteiner code of Warme et al. has average running time comparable to that of the fastest available BI1S implementation, due to Robins. We are, thus, faced with the paradoxical situation that an exact algorithm for an NP-hard problem is competitive in speed with a state of-the-art heuristic for the problem. The main contribution of this paper is a new RST heuristic, which has at its core a recent 3/2 approximation algorithm of Rajagopalan and Vazirani for the metric Steiner tree problem on quasi-bipartite graphs-these are graphs that do not contain edges connecting pairs of Steiner vertices. The RV algorithm is built around the linear programming relaxation of a sophisticated integer program formulation, called the bidirected cut relaxation. Our heuristic achieves a good running time by combining an efficient implementation of the RV algorithm with simple, but powerful geometric reductions. Experiments conducted on both random and real very large scale integrated instances show that the new RST heuristic runs significantly faster than Robins' implementation of BI1S and than the GeoSteiner code. Moreover, the new heuristic typically gives higher-quality solutions than BI1S.

European activities for EDA standardization

Current European activities for standardization in the field of electronic design automation are discussed. The activities concentrate mainly in the areas of system description languages (VHDL), data interchange formats (EDIF), and development environments, (frameworks). It is shown that, in support of these three areas, information modeling and standard interoperability became important areas of investigation. The roles of the European CAD Standardization Initiative (ECSI) and the European CAD Integration Project (ECIP) in the standardization effort are described. >