Fidelity Range Extensions Research Articles

FAST CALCULATION OF 8 × 8 INTEGER DCT IN THE SOFTWARE IMPLEMENTATION OF H.264/AVC

In order to achieve higher compression performance the fidelity range extension (FRExt) amendment was added to the H.264 advanced video coding (AVC) standard. It uses both 4 × 4 and 8 × 8 integer discrete cosine transform (DCT) adaptively in the high profiles. This led to additional complexity of the initial version of the H.264/AVC encoder which had substantially high computational complexity. In this paper, we propose a new algorithm which reduces the computational complexity for software implementation of horizontal 8 × 8 integer DCT by more than 25%. Simulation results indicate 22% reduction in the computation time by using the proposed algorithm.

ULTRA-HD Content Acquisition and Exchange Using HEVC Range Extensions

The introduction of Ultra High Definition Televisions will build upon the growing consumer desire for the highest TV image quality possible. The new High Efficiency Video Coding (HEVC) standard (H.265, MPEG-H) provides the most bandwidth-efficient delivery of HD and UHD content. HEVC was standardized in early 2013 but only addressed consumer applications. In mid 2014, the HEVC Range Extensions (RExt) profiles were standardized to address professional applications. This paper will describe true 4K UHDTV and how it achieves a greater immersive viewing experience than today's HDTV. The paper then will explore the HEVC tool enhancements for contribution and distribution applications, focusing on the 4:2:2 10-bit and 4:2:0 10-bit formats. To give a sense of picture quality versus bandwidth requirements, three experimental lab tests are discussed: UHDTV1 (3840x2160) content is HEVC-compressed and compared with a down-scaled 1080p HD version that is HEVCcompressed and then up-scaled back to UHDTV1 resolution, HEVC RExt is compared against AVC Fidelity Range Extensions for UHDTV1, and the impact of higher frame rates on the bitrate required for UHDTV1 is investigated.

Mode-Dependent Templates and Scan Order for H.264/AVC-Based Intra Lossless Coding

In H.264/advanced video coding (AVC), lossless coding and lossy coding share the same entropy coding module. However, the entropy coders in the H.264/AVC standard were original designed for lossy video coding and do not yield adequate performance for lossless video coding. In this paper, we analyze the problem with the current lossless coding scheme and propose a mode-dependent template (MD-template) based method for intra lossless coding. By exploring the statistical redundancy of the prediction residual in the H.264/AVC intra prediction modes, more zero coefficients are generated. By designing a new scan order for each MD-template, the scanned coefficients sequence fits the H.264/AVC entropy coders better. A fast implementation algorithm is also designed. With little computation increase, experimental results confirm that the proposed fast algorithm achieves about 7.2% bit saving compared with the current H.264/AVC fidelity range extensions high profile.

An 8×8/4×4 Adaptive Hadamard Transform Based FME VLSI Architecture for 4K×2K H.264/AVC Encoder

Fidelity Range Extension (FRExt) (i.e. High Profile) was added to the H.264/AVC recommendation in the second version. One of the features included in FRExt is the Adaptive Block-size Transform (ABT). In order to conform to the FRExt, a Fractional Motion Estimation (FME) architecture is proposed to support the 8×8/4×4 adaptive Hadamard Transform (8×8/4×4 AHT). The 8×8/4×4 AHT circuit contributes to higher throughput and encoding performance. In order to increase the utilization of SATD (Sum of Absolute Transformed Difference) Generator (SG) in unit time, the proposed architecture employs two 8-pel interpolators (IP) to time-share one SG. These two IPs can work in turn to provide the available data continuously to the SG, which increases the data throughput and significantly reduces the cycles that are needed to process one Macroblock. Furthermore, this architecture also exploits the linear feature of Hadamard Transform to generate the quarter-pel SATD. This method could help to shorten the long datapath in the second-step of two-iteration FME algorithm. Finally, experimental results show that this architecture could be used in the applications requiring different performances by adjusting the supported modes and operation frequency. It can support the real-time encoding of the seven-mode 4K×2K@24fps or six-mode 4K×2K@30fps video sequences.

Register Length Analysis and VLSI Optimization of VBS Hadamard Transform in H.264/AVC

Fidelity range extensions of H.264/AVC adopt variable block size (VBS) transform techniques to employ 8 × 8/4 × 4 Hadamard transforms adaptively during the fractional motion estimation. In this literature, the hardwired VBS Hadamard transform accelerator is developed with the following contributions: 1) developed a hardware reusing scheme between 8 × 8 and 4 × 4 transforms within the architecture design; 2) devised the intermediate bit-truncation algorithm to reduce the hardware cost while maintaining the computational precision well; and 3) reduced the bit-width of sum of absolute transformed differences (SATD) value as compared to the primitive implementation, resulting in optimization in both power and hardware cost for the SATD generator implementation. With TSMC 0.18 μm CMOS technology, the experiments demonstrate that for each VBS Hadamard transform engine, 13.0-30.4% saving in hardware cost and 12.6-32.4% saving in power consumption are achieved, whereas the incurred coding quality loss is less than 0.2089 dB in terms of BDPSNR. From the aspect of the whole encoder implementation, and considering the parallelism in searching factional pixel candidates, the proposed strategies garner 2.0 3.9% overall gate count reduction.

Performance analysis, parameter selection and extensions to H.264/AVC FRExt for high resolution video coding

H.264/AVC FRExt (Fidelity Range Extensions) and Motion JPEG 2000 are the current respective inter-frame and intra-frame coding standards for high resolution (HR) (e.g., 4096 × 2160) visual signals. It is commonly believed that an inter-frame method could achieve higher coding efficiency compared with an intra-frame one, due to the exploitation of video temporal redundancy. However, Motion JPEG 2000 has been selected as the digital cinema compression standard, and some existing work has demonstrated that JPEG 2000 is more suitable at HR situations. In this paper, we compare the rate–distortion (R–D) performance of these two different schemes and give more insight from both theoretical and experimental point of view. We derive an entropy-based R–D model to analyze the test results and the impact of residual entropy and quantization for inter-frame coding. Several extensions are introduced into H.264/AVC FRExt for HR video content for better performance. Experimental results show that these extensions lead to significantly higher coding efficiency and make our extended version more suitable for HR video coding

A high-throughput ASIC processor for 8×8 transform coding in H.264/AVC

In July 2004, a new amendment called Fidelity Range Extensions (FRExt) was added to the H.264/AVC as a standardization initiative motivated by the rapidly growing demands when coding higher-fidelity video material. One improvement present in the FRExt is the inclusion of a new 8×8 integer transform that only makes use of additions and shifters to avoid mismatches between encoders and decoders. This paper presents a processor with pipeline architecture for real-time implementation of the complete process for the 8×8 Transform Coding in H.264: forward 8×8 integer transform, quantization and scaling, re-scaling, inverse 8×8 integer transform and reconstruction of the image block. This architecture has been conceived with the aim of achieving a high operation frequency and high throughput without increasing the hardware complexity. In order to achieve an efficient implementation, hardware solutions have been developed for the different circuit modules. 8×8 forward and inverse transforms are calculated using the separability property with architecture more suitable for pipeline schemes made up of two 1D processors and a transpose register array. New expressions for forward quantization and scaling are presented allowing efficient hardware implementation by avoiding the sign conversion. The inverse quantization has also been optimized in terms of hardware complexity by minimizing the involved arithmetic operations. Furthermore, an exhaustive analysis in the dynamic range of the datapath is made to fix the optimum bus widths with the aim of reducing the size of the circuit while avoiding overflow. Finally, the critical paths of the various computing units have been carefully analyzed and balanced using a pipeline scheme in order to maximize the operation frequency without introducing an excessive latency. A prototype with the proposed architecture has been synthesized in a 130 nm HCMOS technology process, which achieves a maximum speed of 330 MHz with a throughput of 2640 Mpixels/s.

Improved CAVLC for H.264/AVC Lossless Intra-Coding

Context-based adaptive variable length coding (CAVLC) for the H.264/advanced video coding (AVC) standard was originally designed for lossy video coding, and as such does not yield adequate performance for lossless video coding. In this paper, we propose an improved CAVLC for lossless intra-coding by considering the statistical differences in residual data between lossy and lossless coding. From experimental results, we confirm that the proposed method provides approximately 9% bit saving in terms of a compression ratio compared with the current H.264/AVC fidelity range extensions high profile.

A High Throughput Multiple Transform Architecture for H.264/AVC Fidelity Range Extensions

In this paper, a high throughput multiple transform architecture for H.264 Fidelity Range Extensions (FRExt) is proposed. New techniques are adopted which (1) regularize the 8×8 integer forward and inverse DCT transform matrices, (2) divide them into four 4 × 4 sub-matrices so that simple fast butterfly algorithm can be used, (3) because of the similarity of the sub-matrices, mixed butterflies are proposed that all the sub-matrices of 8 × 8 and matrices of 4×4 forward DCT (FDCT), inverse DCT (IDCT) and Hadamard transform can be merged together. Based on these techniques, a hardware architecture is realized which can achieve throughput of 1.488Gpixel/s when processing either 4×4 or 8×8 transform. With such high throughput, the design can satisfy the critical requirement of the real-time multi-transform processing of High Definition (HD) applications such as High Definition DVD (HD-DVD) (1920x1080@60Hz) in H.264/AVC FRExt. This work has been synthesized using Rohm 0.18um library. The design can work on a frequency of 93MHz and throughput of 1.488Gpixel/s with a cost of 56440 gates.

Fast 2-Dimensional 8 x 8 Integer Transform Algorithm Design for H.264/AVC Fidelity Range Extensions

In this letter, efficient two-dimensional (2-D) fast algorithms for realizations of 8 × 8 forward and inverse integer transforms in H.264/AVC fidelity range extensions (FRExt) are proposed. Based on matrix factorizations with Kronecker product and direct sum operations, efficient fast 2-D 8 × 8 forward and inverse integer transforms can be derived from the one-dimensional (1-D) fast 8 × 8 forward and inverse integer transforms through matrix operations. The proposed fast 2-D 8 × 8 forward and inverse integer transform designs don't require transpose memory in hardware realizations. The fast 2-D 8 × 8 integer transforms require fewer latency delays and provide a larger throughput rate than the row-column based method. With regular modularity, the proposed fast algorithms are suitable for VLSI implementations to achieve H.264/AVC FRExt high-profile signal processing.

The H.264/MPEG4 advanced video coding standard and its applications

H.264/MPEG4-AVC is the latest video coding standard of the ITU-T video coding experts group (VCEG) and the ISO/IEC moving picture experts group (MPEG). H.264/MPEG4-AVC has recently become the most widely accepted video coding standard since the deployment of MPEG2 at the dawn of digital television, and it may soon overtake MPEG2 in common use. It covers all common video applications ranging from mobile services and videoconferencing to IPTV, HDTV, and HD video storage. This article discusses the technology behind the new H.264/MPEG4-AVC standard, focusing on the main distinct features of its core coding technology and its first set of extensions, known as the fidelity range extensions (FRExt). In addition, this article also discusses the current status of adoption and deployment of the new standard in various application areas